mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-19 09:04:51 +08:00
a5b7063f6d
Convert the Qualcomm MSM Serial UARTDM bindings to DT Schema. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220405063451.12011-8-krzysztof.kozlowski@linaro.org
113 lines
2.8 KiB
YAML
113 lines
2.8 KiB
YAML
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/serial/qcom,msm-uartdm.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Qualcomm MSM Serial UARTDM
|
|
|
|
maintainers:
|
|
- Andy Gross <agross@kernel.org>
|
|
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
|
|
description: |
|
|
The MSM serial UARTDM hardware is designed for high-speed use cases where the
|
|
transmit and/or receive channels can be offloaded to a dma-engine. From a
|
|
software perspective it's mostly compatible with the MSM serial UART except
|
|
that it supports reading and writing multiple characters at a time.
|
|
|
|
Note:: Aliases may be defined to ensure the correct ordering of the UARTs.
|
|
The alias serialN will result in the UART being assigned port N. If any
|
|
serialN alias exists, then an alias must exist for each enabled UART. The
|
|
serialN aliases should be in a .dts file instead of in a .dtsi file.
|
|
|
|
properties:
|
|
compatible:
|
|
items:
|
|
- enum:
|
|
- qcom,msm-uartdm-v1.1
|
|
- qcom,msm-uartdm-v1.2
|
|
- qcom,msm-uartdm-v1.3
|
|
- qcom,msm-uartdm-v1.4
|
|
- const: qcom,msm-uartdm
|
|
|
|
clocks:
|
|
maxItems: 2
|
|
|
|
clock-names:
|
|
items:
|
|
- const: core
|
|
- const: iface
|
|
|
|
dmas:
|
|
maxItems: 2
|
|
|
|
dma-names:
|
|
items:
|
|
- const: tx
|
|
- const: rx
|
|
|
|
interrupts:
|
|
maxItems: 1
|
|
|
|
qcom,rx-crci:
|
|
$ref: /schemas/types.yaml#/definitions/uint32
|
|
description:
|
|
Identificator for Client Rate Control Interface to be used with RX DMA
|
|
channel. Required when using DMA for reception with UARTDM v1.3 and
|
|
below.
|
|
|
|
qcom,tx-crci:
|
|
$ref: /schemas/types.yaml#/definitions/uint32
|
|
description:
|
|
Identificator for Client Rate Control Interface to be used with TX DMA
|
|
channel. Required when using DMA for transmission with UARTDM v1.3 and
|
|
below.
|
|
|
|
reg:
|
|
minItems: 1
|
|
items:
|
|
- description: Main control registers
|
|
- description: An optional second register location shall specify the GSBI control region.
|
|
|
|
required:
|
|
- compatible
|
|
- clock-names
|
|
- clocks
|
|
- interrupts
|
|
- reg
|
|
|
|
unevaluatedProperties: false
|
|
|
|
allOf:
|
|
- $ref: /schemas/serial/serial.yaml#
|
|
|
|
- if:
|
|
properties:
|
|
compatible:
|
|
contains:
|
|
const: qcom,msm-uartdm-v1.3
|
|
then:
|
|
properties:
|
|
reg:
|
|
minItems: 2
|
|
else:
|
|
properties:
|
|
reg:
|
|
maxItems: 1
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
serial@f991e000 {
|
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
|
reg = <0xf991e000 0x1000>;
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>;
|
|
clock-names = "core", "iface";
|
|
dmas = <&dma0 0>, <&dma0 1>;
|
|
dma-names = "tx", "rx";
|
|
};
|