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Document RZ/V2L (R9A07G054) IRQC bindings. The RZ/V2L IRQC block is
identical to one found on the RZ/G2L SoC. No driver changes are
required as generic compatible string "renesas,rzg2l-irqc" will be
used as a fallback.
While at it, update the comment "# RZ/G2L" to "# RZ/G2{L,LC}" for
"renesas,r9a07g044-irqc" compatible string as both RZ/G2L and
RZ/G2LC SoC's use the common SoC DTSI and have the same IRQC block.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220718193745.7472-1-prabhakar.mahadev-lad.rj@bp.renesas.com
135 lines
4.8 KiB
YAML
135 lines
4.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)
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maintainers:
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- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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- Geert Uytterhoeven <geert+renesas@glider.be>
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description: |
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IA55 performs various interrupt controls including synchronization for the external
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interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral
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interrupts output by each IP. And it notifies the interrupt to the GIC
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- IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
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- GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
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- NMI edge select (NMI is not treated as NMI exception and supports fall edge and
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stand-up edge detection interrupts)
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
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properties:
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compatible:
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items:
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- enum:
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- renesas,r9a07g044-irqc # RZ/G2{L,LC}
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- renesas,r9a07g054-irqc # RZ/V2L
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- const: renesas,rzg2l-irqc
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'#interrupt-cells':
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description: The first cell should contain external interrupt number (IRQ0-7) and the
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second cell is used to specify the flag.
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const: 2
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'#address-cells':
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const: 0
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interrupt-controller: true
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reg:
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maxItems: 1
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interrupts:
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maxItems: 41
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: clk
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- const: pclk
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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required:
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- compatible
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- '#interrupt-cells'
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- '#address-cells'
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- interrupt-controller
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- reg
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- interrupts
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- clocks
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- clock-names
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- power-domains
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- resets
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/r9a07g044-cpg.h>
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irqc: interrupt-controller@110a0000 {
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compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
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reg = <0x110a0000 0x10000>;
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#interrupt-cells = <2>;
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#address-cells = <0>;
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interrupt-controller;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
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<&cpg CPG_MOD R9A07G044_IA55_PCLK>;
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clock-names = "clk", "pclk";
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power-domains = <&cpg>;
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resets = <&cpg R9A07G044_IA55_RESETN>;
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};
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