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af44d180e3
i.MX8MN has different speed grade definition compared to
i.MX8MQ/i.MX8MM, when fuses are NOT written, the default
speed_grade should be set to minimum available OPP defined
in DT which is 1.2GHz, the corresponding speed_grade value
should be 0xb.
Fixes: 5b8010ba70 ("cpufreq: imx-cpufreq-dt: Add i.MX8MN support")
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
105 lines
3.0 KiB
C
105 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 NXP
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*/
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#include <linux/cpu.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/nvmem-consumer.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_opp.h>
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#include <linux/slab.h>
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#define OCOTP_CFG3_SPEED_GRADE_SHIFT 8
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#define OCOTP_CFG3_SPEED_GRADE_MASK (0x3 << 8)
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#define IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK (0xf << 8)
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#define OCOTP_CFG3_MKT_SEGMENT_SHIFT 6
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#define OCOTP_CFG3_MKT_SEGMENT_MASK (0x3 << 6)
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/* cpufreq-dt device registered by imx-cpufreq-dt */
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static struct platform_device *cpufreq_dt_pdev;
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static struct opp_table *cpufreq_opp_table;
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static int imx_cpufreq_dt_probe(struct platform_device *pdev)
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{
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struct device *cpu_dev = get_cpu_device(0);
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u32 cell_value, supported_hw[2];
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int speed_grade, mkt_segment;
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int ret;
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ret = nvmem_cell_read_u32(cpu_dev, "speed_grade", &cell_value);
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if (ret)
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return ret;
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if (of_machine_is_compatible("fsl,imx8mn"))
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speed_grade = (cell_value & IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK)
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>> OCOTP_CFG3_SPEED_GRADE_SHIFT;
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else
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speed_grade = (cell_value & OCOTP_CFG3_SPEED_GRADE_MASK)
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>> OCOTP_CFG3_SPEED_GRADE_SHIFT;
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mkt_segment = (cell_value & OCOTP_CFG3_MKT_SEGMENT_MASK) >> OCOTP_CFG3_MKT_SEGMENT_SHIFT;
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/*
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* Early samples without fuses written report "0 0" which may NOT
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* match any OPP defined in DT. So clamp to minimum OPP defined in
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* DT to avoid warning for "no OPPs".
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*
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* Applies to i.MX8M series SoCs.
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*/
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if (mkt_segment == 0 && speed_grade == 0) {
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if (of_machine_is_compatible("fsl,imx8mm") ||
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of_machine_is_compatible("fsl,imx8mq"))
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speed_grade = 1;
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if (of_machine_is_compatible("fsl,imx8mn"))
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speed_grade = 0xb;
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}
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supported_hw[0] = BIT(speed_grade);
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supported_hw[1] = BIT(mkt_segment);
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dev_info(&pdev->dev, "cpu speed grade %d mkt segment %d supported-hw %#x %#x\n",
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speed_grade, mkt_segment, supported_hw[0], supported_hw[1]);
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cpufreq_opp_table = dev_pm_opp_set_supported_hw(cpu_dev, supported_hw, 2);
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if (IS_ERR(cpufreq_opp_table)) {
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ret = PTR_ERR(cpufreq_opp_table);
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dev_err(&pdev->dev, "Failed to set supported opp: %d\n", ret);
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return ret;
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}
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cpufreq_dt_pdev = platform_device_register_data(
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&pdev->dev, "cpufreq-dt", -1, NULL, 0);
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if (IS_ERR(cpufreq_dt_pdev)) {
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dev_pm_opp_put_supported_hw(cpufreq_opp_table);
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ret = PTR_ERR(cpufreq_dt_pdev);
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dev_err(&pdev->dev, "Failed to register cpufreq-dt: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static int imx_cpufreq_dt_remove(struct platform_device *pdev)
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{
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platform_device_unregister(cpufreq_dt_pdev);
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dev_pm_opp_put_supported_hw(cpufreq_opp_table);
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return 0;
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}
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static struct platform_driver imx_cpufreq_dt_driver = {
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.probe = imx_cpufreq_dt_probe,
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.remove = imx_cpufreq_dt_remove,
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.driver = {
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.name = "imx-cpufreq-dt",
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},
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};
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module_platform_driver(imx_cpufreq_dt_driver);
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MODULE_ALIAS("platform:imx-cpufreq-dt");
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MODULE_DESCRIPTION("Freescale i.MX cpufreq speed grading driver");
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MODULE_LICENSE("GPL v2");
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