Linus Walleij b14cbdfd46 clk: ux500: Add driver for the reset portions of PRCC ... The Ux500 PRCC (peripheral reset and clock controller) can also control reset of the IP blocks, not just clocks. As the PRCC is probed as a clock controller and we have other platforms implementing combined clock and reset controllers, follow this pattern and implement the PRCC rest controller as part of the clock driver. The reset controller needs to be selected from the machine as Ux500 has traditionally selected its mandatory subsystem prerequisites from there. Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20210921184803.1757916-2-linus.walleij@linaro.org Acked-by: Ulf Hansson <ulf.hansson@linaro.org> [sboyd@kernel.org: Dropped allocation error message] Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2021-10-26 18:06:05 -07:00
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cpu-db8500.c	mfd: db8500-prcmu: Support U8420-sysclk firmware	2019-11-11 08:45:04 +00:00
db8500-regs.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 194	2019-05-30 11:29:22 -07:00
Kconfig	clk: ux500: Add driver for the reset portions of PRCC	2021-10-26 18:06:05 -07:00
Makefile	treewide: Add SPDX license identifier - Makefile/Kconfig	2019-05-21 10:50:46 +02:00
platsmp.c	ARM: ux500: make ux500_cpu_die static	2021-04-01 22:30:49 +02:00
pm_domains.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 194	2019-05-30 11:29:22 -07:00
pm_domains.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 194	2019-05-30 11:29:22 -07:00
pm.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 194	2019-05-30 11:29:22 -07:00