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f6b1340dc7
The for-loop iterates with a u8 loop counter i and compares this
with the loop upper limit of num_parents that is an int type.
There is a potential infinite loop if num_parents is larger than
the u8 loop counter. Fix this by making the loop counter the same
type as num_parents. Also make num_parents an unsigned int to
match the return type of the call to clk_hw_get_num_parents.
Addresses-Coverity: ("Infinite loop")
Fixes: 734d82f4a6 ("clk: uniphier: add core support code for UniPhier clock driver")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Reviewed-by: Masahiro Yamada <masahiroy@kernel.org>
Link: https://lore.kernel.org/r/20210409090104.629722-1-colin.king@canonical.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
87 lines
2.0 KiB
C
87 lines
2.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/regmap.h>
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#include "clk-uniphier.h"
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struct uniphier_clk_mux {
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struct clk_hw hw;
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struct regmap *regmap;
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unsigned int reg;
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const unsigned int *masks;
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const unsigned int *vals;
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};
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#define to_uniphier_clk_mux(_hw) container_of(_hw, struct uniphier_clk_mux, hw)
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static int uniphier_clk_mux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw);
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return regmap_write_bits(mux->regmap, mux->reg, mux->masks[index],
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mux->vals[index]);
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}
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static u8 uniphier_clk_mux_get_parent(struct clk_hw *hw)
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{
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struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw);
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unsigned int num_parents = clk_hw_get_num_parents(hw);
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int ret;
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unsigned int val;
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unsigned int i;
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ret = regmap_read(mux->regmap, mux->reg, &val);
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if (ret)
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return ret;
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for (i = 0; i < num_parents; i++)
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if ((mux->masks[i] & val) == mux->vals[i])
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return i;
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return -EINVAL;
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}
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static const struct clk_ops uniphier_clk_mux_ops = {
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.determine_rate = __clk_mux_determine_rate,
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.set_parent = uniphier_clk_mux_set_parent,
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.get_parent = uniphier_clk_mux_get_parent,
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};
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struct clk_hw *uniphier_clk_register_mux(struct device *dev,
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struct regmap *regmap,
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const char *name,
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const struct uniphier_clk_mux_data *data)
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{
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struct uniphier_clk_mux *mux;
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struct clk_init_data init;
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int ret;
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mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &uniphier_clk_mux_ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_names = data->parent_names;
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init.num_parents = data->num_parents;
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mux->regmap = regmap;
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mux->reg = data->reg;
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mux->masks = data->masks;
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mux->vals = data->vals;
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mux->hw.init = &init;
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ret = devm_clk_hw_register(dev, &mux->hw);
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if (ret)
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return ERR_PTR(ret);
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return &mux->hw;
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}
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