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a0caa19711
make allmodconfig && make W=1 C=1 reports: WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/cxl/core/cxl_core.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/cxl/cxl_pci.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/cxl/cxl_mem.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/cxl/cxl_acpi.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/cxl/cxl_pmem.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/cxl/cxl_port.o Add the missing invocations of the MODULE_DESCRIPTION() macro. Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://patch.msgid.link/20240607-md-drivers-cxl-v2-1-0c61d95ee7a7@quicinc.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
216 lines
5.3 KiB
C
216 lines
5.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2022 Intel Corporation. All rights reserved. */
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include "cxlmem.h"
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#include "cxlpci.h"
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/**
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* DOC: cxl port
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*
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* The port driver enumerates dport via PCI and scans for HDM
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* (Host-managed-Device-Memory) decoder resources via the
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* @component_reg_phys value passed in by the agent that registered the
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* port. All descendant ports of a CXL root port (described by platform
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* firmware) are managed in this drivers context. Each driver instance
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* is responsible for tearing down the driver context of immediate
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* descendant ports. The locking for this is validated by
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* CONFIG_PROVE_CXL_LOCKING.
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*
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* The primary service this driver provides is presenting APIs to other
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* drivers to utilize the decoders, and indicating to userspace (via bind
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* status) the connectivity of the CXL.mem protocol throughout the
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* PCIe topology.
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*/
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static void schedule_detach(void *cxlmd)
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{
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schedule_cxl_memdev_detach(cxlmd);
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}
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static int discover_region(struct device *dev, void *root)
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{
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struct cxl_endpoint_decoder *cxled;
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int rc;
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if (!is_endpoint_decoder(dev))
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return 0;
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cxled = to_cxl_endpoint_decoder(dev);
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if ((cxled->cxld.flags & CXL_DECODER_F_ENABLE) == 0)
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return 0;
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if (cxled->state != CXL_DECODER_STATE_AUTO)
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return 0;
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/*
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* Region enumeration is opportunistic, if this add-event fails,
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* continue to the next endpoint decoder.
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*/
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rc = cxl_add_to_region(root, cxled);
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if (rc)
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dev_dbg(dev, "failed to add to region: %#llx-%#llx\n",
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cxled->cxld.hpa_range.start, cxled->cxld.hpa_range.end);
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return 0;
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}
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static int cxl_switch_port_probe(struct cxl_port *port)
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{
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struct cxl_hdm *cxlhdm;
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int rc;
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/* Cache the data early to ensure is_visible() works */
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read_cdat_data(port);
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rc = devm_cxl_port_enumerate_dports(port);
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if (rc < 0)
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return rc;
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cxl_switch_parse_cdat(port);
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cxlhdm = devm_cxl_setup_hdm(port, NULL);
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if (!IS_ERR(cxlhdm))
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return devm_cxl_enumerate_decoders(cxlhdm, NULL);
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if (PTR_ERR(cxlhdm) != -ENODEV) {
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dev_err(&port->dev, "Failed to map HDM decoder capability\n");
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return PTR_ERR(cxlhdm);
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}
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if (rc == 1) {
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dev_dbg(&port->dev, "Fallback to passthrough decoder\n");
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return devm_cxl_add_passthrough_decoder(port);
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}
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dev_err(&port->dev, "HDM decoder capability not found\n");
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return -ENXIO;
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}
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static int cxl_endpoint_port_probe(struct cxl_port *port)
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{
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struct cxl_endpoint_dvsec_info info = { .port = port };
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struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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struct cxl_hdm *cxlhdm;
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struct cxl_port *root;
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int rc;
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rc = cxl_dvsec_rr_decode(cxlds->dev, cxlds->cxl_dvsec, &info);
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if (rc < 0)
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return rc;
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cxlhdm = devm_cxl_setup_hdm(port, &info);
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if (IS_ERR(cxlhdm)) {
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if (PTR_ERR(cxlhdm) == -ENODEV)
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dev_err(&port->dev, "HDM decoder registers not found\n");
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return PTR_ERR(cxlhdm);
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}
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/* Cache the data early to ensure is_visible() works */
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read_cdat_data(port);
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cxl_endpoint_parse_cdat(port);
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get_device(&cxlmd->dev);
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rc = devm_add_action_or_reset(&port->dev, schedule_detach, cxlmd);
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if (rc)
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return rc;
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rc = cxl_hdm_decode_init(cxlds, cxlhdm, &info);
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if (rc)
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return rc;
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rc = devm_cxl_enumerate_decoders(cxlhdm, &info);
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if (rc)
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return rc;
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/*
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* This can't fail in practice as CXL root exit unregisters all
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* descendant ports and that in turn synchronizes with cxl_port_probe()
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*/
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struct cxl_root *cxl_root __free(put_cxl_root) = find_cxl_root(port);
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root = &cxl_root->port;
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/*
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* Now that all endpoint decoders are successfully enumerated, try to
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* assemble regions from committed decoders
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*/
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device_for_each_child(&port->dev, root, discover_region);
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return 0;
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}
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static int cxl_port_probe(struct device *dev)
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{
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struct cxl_port *port = to_cxl_port(dev);
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if (is_cxl_endpoint(port))
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return cxl_endpoint_port_probe(port);
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return cxl_switch_port_probe(port);
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}
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static ssize_t CDAT_read(struct file *filp, struct kobject *kobj,
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struct bin_attribute *bin_attr, char *buf,
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loff_t offset, size_t count)
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{
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struct device *dev = kobj_to_dev(kobj);
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struct cxl_port *port = to_cxl_port(dev);
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if (!port->cdat_available)
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return -ENXIO;
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if (!port->cdat.table)
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return 0;
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return memory_read_from_buffer(buf, count, &offset,
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port->cdat.table,
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port->cdat.length);
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}
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static BIN_ATTR_ADMIN_RO(CDAT, 0);
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static umode_t cxl_port_bin_attr_is_visible(struct kobject *kobj,
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struct bin_attribute *attr, int i)
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{
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struct device *dev = kobj_to_dev(kobj);
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struct cxl_port *port = to_cxl_port(dev);
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if ((attr == &bin_attr_CDAT) && port->cdat_available)
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return attr->attr.mode;
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return 0;
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}
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static struct bin_attribute *cxl_cdat_bin_attributes[] = {
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&bin_attr_CDAT,
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NULL,
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};
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static struct attribute_group cxl_cdat_attribute_group = {
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.bin_attrs = cxl_cdat_bin_attributes,
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.is_bin_visible = cxl_port_bin_attr_is_visible,
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};
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static const struct attribute_group *cxl_port_attribute_groups[] = {
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&cxl_cdat_attribute_group,
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NULL,
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};
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static struct cxl_driver cxl_port_driver = {
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.name = "cxl_port",
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.probe = cxl_port_probe,
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.id = CXL_DEVICE_PORT,
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.drv = {
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.dev_groups = cxl_port_attribute_groups,
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},
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};
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module_cxl_driver(cxl_port_driver);
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MODULE_DESCRIPTION("CXL: Port enumeration and services");
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MODULE_LICENSE("GPL v2");
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MODULE_IMPORT_NS(CXL);
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MODULE_ALIAS_CXL(CXL_DEVICE_PORT);
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