Li Ming 8c251c5ab1 cxl/pci: Get AER capability address from RCRB only for RCH dport ... cxl_setup_parent_dport() needs to get RCH dport AER capability address from RCRB to disable AER interrupt. The function does not check if dport is RCH dport, it will get a wrong pci_host_bridge structure by dport_dev in VH case because dport_dev points to a pci device(RP or switch DSP) rather than a pci host bridge device. Fixes: f05fd10d13 ("cxl/pci: Add RCH downstream port AER register discovery") Signed-off-by: Li Ming <ming4.li@intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Tested-by: Ira Weiny <ira.weiny@intel.com> Tested-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20240809082750.3015641-2-ming4.li@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>		2024-08-09 15:13:07 -07:00
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core	cxl/pci: Get AER capability address from RCRB only for RCH dport	2024-08-09 15:13:07 -07:00
acpi.c	Merge branch 'for-6.11/xor_fixes' into cxl-for-next	2024-07-11 16:47:47 -07:00
cxl.h	CXL for v6.11 merge window	2024-07-28 09:33:28 -07:00
cxlmem.h	CXL for v6.11 merge window	2024-07-28 09:33:28 -07:00
cxlpci.h	PCI/CXL: Move CXL Vendor ID to pci_ids.h	2024-05-08 13:18:33 -05:00
Kconfig	cxl: Fix use of phys_to_target_node() for x86	2024-04-30 10:43:48 -07:00
Makefile	cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operation	2022-11-30 16:30:47 -08:00
mem.c	CXL for v6.11 merge window	2024-07-28 09:33:28 -07:00
pci.c	cxl: add missing MODULE_DESCRIPTION() macros	2024-07-02 12:52:26 -07:00
pmem.c	cxl: add missing MODULE_DESCRIPTION() macros	2024-07-02 12:52:26 -07:00
pmu.h	cxl/pci: Find and register CXL PMU devices	2023-05-30 11:20:35 -07:00
port.c	cxl: add missing MODULE_DESCRIPTION() macros	2024-07-02 12:52:26 -07:00
security.c	Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxl	2023-06-25 17:16:51 -07:00