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https://mirrors.bfsu.edu.cn/git/linux.git
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7235d9e48f
The current codebase makes use of the zero-length array language
extension to the C90 standard, but the preferred mechanism to declare
variable-length types such as these ones is a flexible array member[1][2],
introduced in C99:
struct foo {
int stuff;
struct boo array[];
};
By making use of the mechanism above, we will get a compiler warning
in case the flexible array does not occur last in the structure, which
will help us prevent some kind of undefined behavior bugs from being
inadvertently introduced[3] to the codebase from now on.
Also, notice that, dynamic memory allocations won't be affected by
this change:
"Flexible array members have incomplete type, and so the sizeof operator
may not be applied. As a quirk of the original implementation of
zero-length arrays, sizeof evaluates to zero."[1]
This issue was found with the help of Coccinelle.
[1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html
[2] https://github.com/KSPP/linux/issues/21
[3] commit 7649773293
("cxgb3/l2t: Fix undefined behaviour")
Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
634 lines
16 KiB
C
634 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/ssbi.h>
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#include <linux/regmap.h>
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#include <linux/of_platform.h>
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#include <linux/mfd/core.h>
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#define SSBI_REG_ADDR_IRQ_BASE 0x1BB
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#define SSBI_REG_ADDR_IRQ_ROOT (SSBI_REG_ADDR_IRQ_BASE + 0)
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#define SSBI_REG_ADDR_IRQ_M_STATUS1 (SSBI_REG_ADDR_IRQ_BASE + 1)
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#define SSBI_REG_ADDR_IRQ_M_STATUS2 (SSBI_REG_ADDR_IRQ_BASE + 2)
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#define SSBI_REG_ADDR_IRQ_M_STATUS3 (SSBI_REG_ADDR_IRQ_BASE + 3)
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#define SSBI_REG_ADDR_IRQ_M_STATUS4 (SSBI_REG_ADDR_IRQ_BASE + 4)
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#define SSBI_REG_ADDR_IRQ_BLK_SEL (SSBI_REG_ADDR_IRQ_BASE + 5)
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#define SSBI_REG_ADDR_IRQ_IT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 6)
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#define SSBI_REG_ADDR_IRQ_CONFIG (SSBI_REG_ADDR_IRQ_BASE + 7)
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#define SSBI_REG_ADDR_IRQ_RT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 8)
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#define PM8821_SSBI_REG_ADDR_IRQ_BASE 0x100
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#define PM8821_SSBI_REG_ADDR_IRQ_MASTER0 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0x30)
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#define PM8821_SSBI_REG_ADDR_IRQ_MASTER1 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0xb0)
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#define PM8821_SSBI_REG(m, b, offset) \
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((m == 0) ? \
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(PM8821_SSBI_REG_ADDR_IRQ_MASTER0 + b + offset) : \
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(PM8821_SSBI_REG_ADDR_IRQ_MASTER1 + b + offset))
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#define PM8821_SSBI_ADDR_IRQ_ROOT(m, b) PM8821_SSBI_REG(m, b, 0x0)
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#define PM8821_SSBI_ADDR_IRQ_CLEAR(m, b) PM8821_SSBI_REG(m, b, 0x01)
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#define PM8821_SSBI_ADDR_IRQ_MASK(m, b) PM8821_SSBI_REG(m, b, 0x08)
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#define PM8821_SSBI_ADDR_IRQ_RT_STATUS(m, b) PM8821_SSBI_REG(m, b, 0x0f)
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#define PM8821_BLOCKS_PER_MASTER 7
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#define PM_IRQF_LVL_SEL 0x01 /* level select */
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#define PM_IRQF_MASK_FE 0x02 /* mask falling edge */
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#define PM_IRQF_MASK_RE 0x04 /* mask rising edge */
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#define PM_IRQF_CLR 0x08 /* clear interrupt */
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#define PM_IRQF_BITS_MASK 0x70
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#define PM_IRQF_BITS_SHIFT 4
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#define PM_IRQF_WRITE 0x80
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#define PM_IRQF_MASK_ALL (PM_IRQF_MASK_FE | \
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PM_IRQF_MASK_RE)
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#define REG_HWREV 0x002 /* PMIC4 revision */
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#define REG_HWREV_2 0x0E8 /* PMIC4 revision 2 */
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#define PM8XXX_NR_IRQS 256
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#define PM8821_NR_IRQS 112
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struct pm_irq_data {
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int num_irqs;
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struct irq_chip *irq_chip;
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void (*irq_handler)(struct irq_desc *desc);
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};
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struct pm_irq_chip {
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struct regmap *regmap;
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spinlock_t pm_irq_lock;
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struct irq_domain *irqdomain;
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unsigned int num_blocks;
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unsigned int num_masters;
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const struct pm_irq_data *pm_irq_data;
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/* MUST BE AT THE END OF THIS STRUCT */
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u8 config[];
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};
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static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp,
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unsigned int *ip)
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{
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int rc;
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spin_lock(&chip->pm_irq_lock);
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rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
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if (rc) {
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pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
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goto bail;
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}
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rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
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if (rc)
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pr_err("Failed Reading Status rc=%d\n", rc);
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bail:
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spin_unlock(&chip->pm_irq_lock);
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return rc;
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}
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static int
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pm8xxx_config_irq(struct pm_irq_chip *chip, unsigned int bp, unsigned int cp)
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{
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int rc;
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spin_lock(&chip->pm_irq_lock);
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rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
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if (rc) {
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pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
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goto bail;
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}
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cp |= PM_IRQF_WRITE;
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rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_CONFIG, cp);
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if (rc)
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pr_err("Failed Configuring IRQ rc=%d\n", rc);
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bail:
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spin_unlock(&chip->pm_irq_lock);
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return rc;
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}
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static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
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{
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int pmirq, irq, i, ret = 0;
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unsigned int bits;
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ret = pm8xxx_read_block_irq(chip, block, &bits);
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if (ret) {
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pr_err("Failed reading %d block ret=%d", block, ret);
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return ret;
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}
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if (!bits) {
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pr_err("block bit set in master but no irqs: %d", block);
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return 0;
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}
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/* Check IRQ bits */
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for (i = 0; i < 8; i++) {
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if (bits & (1 << i)) {
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pmirq = block * 8 + i;
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irq = irq_find_mapping(chip->irqdomain, pmirq);
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generic_handle_irq(irq);
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}
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}
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return 0;
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}
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static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master)
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{
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unsigned int blockbits;
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int block_number, i, ret = 0;
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ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_M_STATUS1 + master,
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&blockbits);
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if (ret) {
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pr_err("Failed to read master %d ret=%d\n", master, ret);
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return ret;
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}
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if (!blockbits) {
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pr_err("master bit set in root but no blocks: %d", master);
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return 0;
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}
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for (i = 0; i < 8; i++)
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if (blockbits & (1 << i)) {
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block_number = master * 8 + i; /* block # */
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ret |= pm8xxx_irq_block_handler(chip, block_number);
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}
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return ret;
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}
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static void pm8xxx_irq_handler(struct irq_desc *desc)
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{
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struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
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struct irq_chip *irq_chip = irq_desc_get_chip(desc);
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unsigned int root;
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int i, ret, masters = 0;
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chained_irq_enter(irq_chip, desc);
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ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_ROOT, &root);
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if (ret) {
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pr_err("Can't read root status ret=%d\n", ret);
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return;
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}
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/* on pm8xxx series masters start from bit 1 of the root */
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masters = root >> 1;
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/* Read allowed masters for blocks. */
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for (i = 0; i < chip->num_masters; i++)
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if (masters & (1 << i))
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pm8xxx_irq_master_handler(chip, i);
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chained_irq_exit(irq_chip, desc);
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}
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static void pm8821_irq_block_handler(struct pm_irq_chip *chip,
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int master, int block)
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{
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int pmirq, irq, i, ret;
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unsigned int bits;
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ret = regmap_read(chip->regmap,
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PM8821_SSBI_ADDR_IRQ_ROOT(master, block), &bits);
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if (ret) {
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pr_err("Reading block %d failed ret=%d", block, ret);
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return;
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}
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/* Convert block offset to global block number */
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block += (master * PM8821_BLOCKS_PER_MASTER) - 1;
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/* Check IRQ bits */
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for (i = 0; i < 8; i++) {
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if (bits & BIT(i)) {
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pmirq = block * 8 + i;
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irq = irq_find_mapping(chip->irqdomain, pmirq);
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generic_handle_irq(irq);
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}
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}
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}
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static inline void pm8821_irq_master_handler(struct pm_irq_chip *chip,
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int master, u8 master_val)
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{
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int block;
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for (block = 1; block < 8; block++)
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if (master_val & BIT(block))
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pm8821_irq_block_handler(chip, master, block);
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}
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static void pm8821_irq_handler(struct irq_desc *desc)
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{
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struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
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struct irq_chip *irq_chip = irq_desc_get_chip(desc);
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unsigned int master;
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int ret;
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chained_irq_enter(irq_chip, desc);
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ret = regmap_read(chip->regmap,
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PM8821_SSBI_REG_ADDR_IRQ_MASTER0, &master);
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if (ret) {
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pr_err("Failed to read master 0 ret=%d\n", ret);
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goto done;
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}
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/* bits 1 through 7 marks the first 7 blocks in master 0 */
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if (master & GENMASK(7, 1))
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pm8821_irq_master_handler(chip, 0, master);
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/* bit 0 marks if master 1 contains any bits */
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if (!(master & BIT(0)))
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goto done;
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ret = regmap_read(chip->regmap,
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PM8821_SSBI_REG_ADDR_IRQ_MASTER1, &master);
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if (ret) {
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pr_err("Failed to read master 1 ret=%d\n", ret);
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goto done;
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}
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pm8821_irq_master_handler(chip, 1, master);
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done:
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chained_irq_exit(irq_chip, desc);
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}
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static void pm8xxx_irq_mask_ack(struct irq_data *d)
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{
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struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
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unsigned int pmirq = irqd_to_hwirq(d);
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u8 block, config;
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block = pmirq / 8;
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config = chip->config[pmirq] | PM_IRQF_MASK_ALL | PM_IRQF_CLR;
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pm8xxx_config_irq(chip, block, config);
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}
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static void pm8xxx_irq_unmask(struct irq_data *d)
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{
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struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
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unsigned int pmirq = irqd_to_hwirq(d);
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u8 block, config;
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block = pmirq / 8;
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config = chip->config[pmirq];
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pm8xxx_config_irq(chip, block, config);
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}
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static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
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unsigned int pmirq = irqd_to_hwirq(d);
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int irq_bit;
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u8 block, config;
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block = pmirq / 8;
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irq_bit = pmirq % 8;
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chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT)
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| PM_IRQF_MASK_ALL;
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if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
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if (flow_type & IRQF_TRIGGER_RISING)
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chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
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if (flow_type & IRQF_TRIGGER_FALLING)
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chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
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} else {
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chip->config[pmirq] |= PM_IRQF_LVL_SEL;
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if (flow_type & IRQF_TRIGGER_HIGH)
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chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
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else
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chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
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}
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config = chip->config[pmirq] | PM_IRQF_CLR;
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return pm8xxx_config_irq(chip, block, config);
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}
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static int pm8xxx_irq_get_irqchip_state(struct irq_data *d,
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enum irqchip_irq_state which,
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bool *state)
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{
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struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
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unsigned int pmirq = irqd_to_hwirq(d);
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unsigned int bits;
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int irq_bit;
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u8 block;
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int rc;
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if (which != IRQCHIP_STATE_LINE_LEVEL)
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return -EINVAL;
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block = pmirq / 8;
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irq_bit = pmirq % 8;
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spin_lock(&chip->pm_irq_lock);
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rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, block);
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if (rc) {
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pr_err("Failed Selecting Block %d rc=%d\n", block, rc);
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goto bail;
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}
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rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
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if (rc) {
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pr_err("Failed Reading Status rc=%d\n", rc);
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goto bail;
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}
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*state = !!(bits & BIT(irq_bit));
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bail:
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spin_unlock(&chip->pm_irq_lock);
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return rc;
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}
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static struct irq_chip pm8xxx_irq_chip = {
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.name = "pm8xxx",
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.irq_mask_ack = pm8xxx_irq_mask_ack,
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.irq_unmask = pm8xxx_irq_unmask,
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.irq_set_type = pm8xxx_irq_set_type,
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.irq_get_irqchip_state = pm8xxx_irq_get_irqchip_state,
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.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
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};
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static void pm8xxx_irq_domain_map(struct pm_irq_chip *chip,
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struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq, unsigned int type)
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{
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irq_domain_set_info(domain, irq, hwirq, chip->pm_irq_data->irq_chip,
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chip, handle_level_irq, NULL, NULL);
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irq_set_noprobe(irq);
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}
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static int pm8xxx_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *data)
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{
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struct pm_irq_chip *chip = domain->host_data;
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struct irq_fwspec *fwspec = data;
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irq_hw_number_t hwirq;
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unsigned int type;
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int ret, i;
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ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
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if (ret)
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return ret;
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for (i = 0; i < nr_irqs; i++)
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pm8xxx_irq_domain_map(chip, domain, virq + i, hwirq + i, type);
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return 0;
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}
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static const struct irq_domain_ops pm8xxx_irq_domain_ops = {
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.alloc = pm8xxx_irq_domain_alloc,
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.free = irq_domain_free_irqs_common,
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.translate = irq_domain_translate_twocell,
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};
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static void pm8821_irq_mask_ack(struct irq_data *d)
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{
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struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
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unsigned int pmirq = irqd_to_hwirq(d);
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u8 block, master;
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int irq_bit, rc;
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block = pmirq / 8;
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master = block / PM8821_BLOCKS_PER_MASTER;
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irq_bit = pmirq % 8;
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block %= PM8821_BLOCKS_PER_MASTER;
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rc = regmap_update_bits(chip->regmap,
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PM8821_SSBI_ADDR_IRQ_MASK(master, block),
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BIT(irq_bit), BIT(irq_bit));
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if (rc) {
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pr_err("Failed to mask IRQ:%d rc=%d\n", pmirq, rc);
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return;
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}
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rc = regmap_update_bits(chip->regmap,
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PM8821_SSBI_ADDR_IRQ_CLEAR(master, block),
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BIT(irq_bit), BIT(irq_bit));
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if (rc)
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pr_err("Failed to CLEAR IRQ:%d rc=%d\n", pmirq, rc);
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}
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static void pm8821_irq_unmask(struct irq_data *d)
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{
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struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
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unsigned int pmirq = irqd_to_hwirq(d);
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int irq_bit, rc;
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u8 block, master;
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block = pmirq / 8;
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master = block / PM8821_BLOCKS_PER_MASTER;
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irq_bit = pmirq % 8;
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block %= PM8821_BLOCKS_PER_MASTER;
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rc = regmap_update_bits(chip->regmap,
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PM8821_SSBI_ADDR_IRQ_MASK(master, block),
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BIT(irq_bit), ~BIT(irq_bit));
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if (rc)
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pr_err("Failed to read/write unmask IRQ:%d rc=%d\n", pmirq, rc);
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|
}
|
|
|
|
static int pm8821_irq_get_irqchip_state(struct irq_data *d,
|
|
enum irqchip_irq_state which,
|
|
bool *state)
|
|
{
|
|
struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
|
|
int rc, pmirq = irqd_to_hwirq(d);
|
|
u8 block, irq_bit, master;
|
|
unsigned int bits;
|
|
|
|
block = pmirq / 8;
|
|
master = block / PM8821_BLOCKS_PER_MASTER;
|
|
irq_bit = pmirq % 8;
|
|
block %= PM8821_BLOCKS_PER_MASTER;
|
|
|
|
rc = regmap_read(chip->regmap,
|
|
PM8821_SSBI_ADDR_IRQ_RT_STATUS(master, block), &bits);
|
|
if (rc) {
|
|
pr_err("Reading Status of IRQ %d failed rc=%d\n", pmirq, rc);
|
|
return rc;
|
|
}
|
|
|
|
*state = !!(bits & BIT(irq_bit));
|
|
|
|
return rc;
|
|
}
|
|
|
|
static struct irq_chip pm8821_irq_chip = {
|
|
.name = "pm8821",
|
|
.irq_mask_ack = pm8821_irq_mask_ack,
|
|
.irq_unmask = pm8821_irq_unmask,
|
|
.irq_get_irqchip_state = pm8821_irq_get_irqchip_state,
|
|
.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
|
|
};
|
|
|
|
static const struct regmap_config ssbi_regmap_config = {
|
|
.reg_bits = 16,
|
|
.val_bits = 8,
|
|
.max_register = 0x3ff,
|
|
.fast_io = true,
|
|
.reg_read = ssbi_reg_read,
|
|
.reg_write = ssbi_reg_write
|
|
};
|
|
|
|
static const struct pm_irq_data pm8xxx_data = {
|
|
.num_irqs = PM8XXX_NR_IRQS,
|
|
.irq_chip = &pm8xxx_irq_chip,
|
|
.irq_handler = pm8xxx_irq_handler,
|
|
};
|
|
|
|
static const struct pm_irq_data pm8821_data = {
|
|
.num_irqs = PM8821_NR_IRQS,
|
|
.irq_chip = &pm8821_irq_chip,
|
|
.irq_handler = pm8821_irq_handler,
|
|
};
|
|
|
|
static const struct of_device_id pm8xxx_id_table[] = {
|
|
{ .compatible = "qcom,pm8018", .data = &pm8xxx_data},
|
|
{ .compatible = "qcom,pm8058", .data = &pm8xxx_data},
|
|
{ .compatible = "qcom,pm8821", .data = &pm8821_data},
|
|
{ .compatible = "qcom,pm8921", .data = &pm8xxx_data},
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
|
|
|
|
static int pm8xxx_probe(struct platform_device *pdev)
|
|
{
|
|
const struct pm_irq_data *data;
|
|
struct regmap *regmap;
|
|
int irq, rc;
|
|
unsigned int val;
|
|
u32 rev;
|
|
struct pm_irq_chip *chip;
|
|
|
|
data = of_device_get_match_data(&pdev->dev);
|
|
if (!data) {
|
|
dev_err(&pdev->dev, "No matching driver data found\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
regmap = devm_regmap_init(&pdev->dev, NULL, pdev->dev.parent,
|
|
&ssbi_regmap_config);
|
|
if (IS_ERR(regmap))
|
|
return PTR_ERR(regmap);
|
|
|
|
/* Read PMIC chip revision */
|
|
rc = regmap_read(regmap, REG_HWREV, &val);
|
|
if (rc) {
|
|
pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
|
|
return rc;
|
|
}
|
|
pr_info("PMIC revision 1: %02X\n", val);
|
|
rev = val;
|
|
|
|
/* Read PMIC chip revision 2 */
|
|
rc = regmap_read(regmap, REG_HWREV_2, &val);
|
|
if (rc) {
|
|
pr_err("Failed to read hw rev 2 reg %d:rc=%d\n",
|
|
REG_HWREV_2, rc);
|
|
return rc;
|
|
}
|
|
pr_info("PMIC revision 2: %02X\n", val);
|
|
rev |= val << BITS_PER_BYTE;
|
|
|
|
chip = devm_kzalloc(&pdev->dev,
|
|
struct_size(chip, config, data->num_irqs),
|
|
GFP_KERNEL);
|
|
if (!chip)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, chip);
|
|
chip->regmap = regmap;
|
|
chip->num_blocks = DIV_ROUND_UP(data->num_irqs, 8);
|
|
chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
|
|
chip->pm_irq_data = data;
|
|
spin_lock_init(&chip->pm_irq_lock);
|
|
|
|
chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
|
|
data->num_irqs,
|
|
&pm8xxx_irq_domain_ops,
|
|
chip);
|
|
if (!chip->irqdomain)
|
|
return -ENODEV;
|
|
|
|
irq_set_chained_handler_and_data(irq, data->irq_handler, chip);
|
|
irq_set_irq_wake(irq, 1);
|
|
|
|
rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
|
|
if (rc) {
|
|
irq_set_chained_handler_and_data(irq, NULL, NULL);
|
|
irq_domain_remove(chip->irqdomain);
|
|
}
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int pm8xxx_remove_child(struct device *dev, void *unused)
|
|
{
|
|
platform_device_unregister(to_platform_device(dev));
|
|
return 0;
|
|
}
|
|
|
|
static int pm8xxx_remove(struct platform_device *pdev)
|
|
{
|
|
int irq = platform_get_irq(pdev, 0);
|
|
struct pm_irq_chip *chip = platform_get_drvdata(pdev);
|
|
|
|
device_for_each_child(&pdev->dev, NULL, pm8xxx_remove_child);
|
|
irq_set_chained_handler_and_data(irq, NULL, NULL);
|
|
irq_domain_remove(chip->irqdomain);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver pm8xxx_driver = {
|
|
.probe = pm8xxx_probe,
|
|
.remove = pm8xxx_remove,
|
|
.driver = {
|
|
.name = "pm8xxx-core",
|
|
.of_match_table = pm8xxx_id_table,
|
|
},
|
|
};
|
|
|
|
static int __init pm8xxx_init(void)
|
|
{
|
|
return platform_driver_register(&pm8xxx_driver);
|
|
}
|
|
subsys_initcall(pm8xxx_init);
|
|
|
|
static void __exit pm8xxx_exit(void)
|
|
{
|
|
platform_driver_unregister(&pm8xxx_driver);
|
|
}
|
|
module_exit(pm8xxx_exit);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("PMIC 8xxx core driver");
|
|
MODULE_VERSION("1.0");
|
|
MODULE_ALIAS("platform:pm8xxx-core");
|