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dd4969a892
Split mvsas driver into multiple source codes, based on the split and function distribution found in Marvell's mvsas update. Signed-off-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
206 lines
5.1 KiB
C
206 lines
5.1 KiB
C
/*
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mv_sas.h - Marvell 88SE6440 SAS/SATA support
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Copyright 2007 Red Hat, Inc.
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Copyright 2008 Marvell. <kewei@marvell.com>
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2,
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or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty
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of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public
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License along with this program; see the file COPYING. If not,
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write to the Free Software Foundation, 675 Mass Ave, Cambridge,
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MA 02139, USA.
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*/
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#ifndef _MV_SAS_H_
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#define _MV_SAS_H_
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/delay.h>
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#include <linux/types.h>
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#include <linux/ctype.h>
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#include <linux/dma-mapping.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/vmalloc.h>
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#include <scsi/libsas.h>
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#include <scsi/scsi_tcq.h>
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#include <scsi/sas_ata.h>
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#include <linux/version.h>
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#include "mv_defs.h"
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#define DRV_NAME "mvsas"
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#define DRV_VERSION "0.5.2"
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#define _MV_DUMP 0
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#define MVS_DISABLE_NVRAM
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#define MVS_DISABLE_MSI
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#define MVS_ID_NOT_MAPPED 0x7f
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#define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width)
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#define for_each_phy(__lseq_mask, __mc, __lseq, __rest) \
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for ((__mc) = (__lseq_mask), (__lseq) = 0; \
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(__mc) != 0 && __rest; \
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(++__lseq), (__mc) >>= 1)
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struct mvs_chip_info {
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u32 n_phy;
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u32 srs_sz;
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u32 slot_width;
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};
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struct mvs_err_info {
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__le32 flags;
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__le32 flags2;
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};
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struct mvs_cmd_hdr {
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__le32 flags; /* PRD tbl len; SAS, SATA ctl */
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__le32 lens; /* cmd, max resp frame len */
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__le32 tags; /* targ port xfer tag; tag */
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__le32 data_len; /* data xfer len */
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__le64 cmd_tbl; /* command table address */
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__le64 open_frame; /* open addr frame address */
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__le64 status_buf; /* status buffer address */
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__le64 prd_tbl; /* PRD tbl address */
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__le32 reserved[4];
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};
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struct mvs_port {
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struct asd_sas_port sas_port;
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u8 port_attached;
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u8 taskfileset;
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u8 wide_port_phymap;
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struct list_head list;
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};
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struct mvs_phy {
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struct mvs_port *port;
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struct asd_sas_phy sas_phy;
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struct sas_identify identify;
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struct scsi_device *sdev;
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u64 dev_sas_addr;
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u64 att_dev_sas_addr;
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u32 att_dev_info;
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u32 dev_info;
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u32 phy_type;
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u32 phy_status;
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u32 irq_status;
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u32 frame_rcvd_size;
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u8 frame_rcvd[32];
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u8 phy_attached;
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enum sas_linkrate minimum_linkrate;
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enum sas_linkrate maximum_linkrate;
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};
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struct mvs_slot_info {
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struct list_head list;
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struct sas_task *task;
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u32 n_elem;
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u32 tx;
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/* DMA buffer for storing cmd tbl, open addr frame, status buffer,
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* and PRD table
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*/
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void *buf;
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dma_addr_t buf_dma;
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#if _MV_DUMP
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u32 cmd_size;
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#endif
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void *response;
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struct mvs_port *port;
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};
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struct mvs_info {
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unsigned long flags;
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/* host-wide lock */
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spinlock_t lock;
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/* our device */
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struct pci_dev *pdev;
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/* enhanced mode registers */
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void __iomem *regs;
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/* peripheral registers */
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void __iomem *peri_regs;
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u8 sas_addr[SAS_ADDR_SIZE];
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/* SCSI/SAS glue */
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struct sas_ha_struct sas;
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struct Scsi_Host *shost;
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/* TX (delivery) DMA ring */
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__le32 *tx;
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dma_addr_t tx_dma;
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/* cached next-producer idx */
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u32 tx_prod;
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/* RX (completion) DMA ring */
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__le32 *rx;
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dma_addr_t rx_dma;
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/* RX consumer idx */
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u32 rx_cons;
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/* RX'd FIS area */
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__le32 *rx_fis;
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dma_addr_t rx_fis_dma;
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/* DMA command header slots */
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struct mvs_cmd_hdr *slot;
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dma_addr_t slot_dma;
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const struct mvs_chip_info *chip;
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u8 tags[MVS_SLOTS];
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struct mvs_slot_info slot_info[MVS_SLOTS];
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/* further per-slot information */
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struct mvs_phy phy[MVS_MAX_PHYS];
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struct mvs_port port[MVS_MAX_PHYS];
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#ifdef MVS_USE_TASKLET
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struct tasklet_struct tasklet;
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#endif
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};
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int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
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void *funcdata);
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int mvs_slave_configure(struct scsi_device *sdev);
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void mvs_scan_start(struct Scsi_Host *shost);
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int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time);
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int mvs_task_exec(struct sas_task *task, const int num, gfp_t gfp_flags);
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int mvs_task_abort(struct sas_task *task);
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void mvs_port_formed(struct asd_sas_phy *sas_phy);
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int mvs_I_T_nexus_reset(struct domain_device *dev);
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void mvs_int_full(struct mvs_info *mvi);
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void mvs_tag_init(struct mvs_info *mvi);
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int mvs_nvram_read(struct mvs_info *mvi, u32 addr, void *buf, u32 buflen);
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int __devinit mvs_hw_init(struct mvs_info *mvi);
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void __devinit mvs_print_info(struct mvs_info *mvi);
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void mvs_hba_interrupt_enable(struct mvs_info *mvi);
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void mvs_hba_interrupt_disable(struct mvs_info *mvi);
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void mvs_detect_porttype(struct mvs_info *mvi, int i);
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u8 mvs_assign_reg_set(struct mvs_info *mvi, struct mvs_port *port);
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void mvs_enable_xmt(struct mvs_info *mvi, int PhyId);
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void __devinit mvs_phy_hacks(struct mvs_info *mvi);
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void mvs_free_reg_set(struct mvs_info *mvi, struct mvs_port *port);
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#endif
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