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dd2adea415
The toolchain defines exactly one of __MIPSEB__ and __MIPSEL__. As a result, simplify the ifdefery a little bit. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8522/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
247 lines
5.6 KiB
ArmAsm
247 lines
5.6 KiB
ArmAsm
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1998, 1999, 2000 by Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 2007 by Maciej W. Rozycki
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* Copyright (C) 2011, 2012 MIPS Technologies, Inc.
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*/
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#include <asm/asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/regdef.h>
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#if LONGSIZE == 4
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#define LONG_S_L swl
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#define LONG_S_R swr
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#else
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#define LONG_S_L sdl
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#define LONG_S_R sdr
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#endif
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#ifdef CONFIG_CPU_MICROMIPS
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#define STORSIZE (LONGSIZE * 2)
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#define STORMASK (STORSIZE - 1)
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#define FILL64RG t8
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#define FILLPTRG t7
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#undef LONG_S
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#define LONG_S LONG_SP
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#else
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#define STORSIZE LONGSIZE
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#define STORMASK LONGMASK
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#define FILL64RG a1
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#define FILLPTRG t0
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#endif
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#define LEGACY_MODE 1
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#define EVA_MODE 2
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/*
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* No need to protect it with EVA #ifdefery. The generated block of code
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* will never be assembled if EVA is not enabled.
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*/
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#define __EVAFY(insn, reg, addr) __BUILD_EVA_INSN(insn##e, reg, addr)
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#define ___BUILD_EVA_INSN(insn, reg, addr) __EVAFY(insn, reg, addr)
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#define EX(insn,reg,addr,handler) \
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.if \mode == LEGACY_MODE; \
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9: insn reg, addr; \
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.else; \
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9: ___BUILD_EVA_INSN(insn, reg, addr); \
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.endif; \
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.section __ex_table,"a"; \
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PTR 9b, handler; \
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.previous
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.macro f_fill64 dst, offset, val, fixup, mode
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EX(LONG_S, \val, (\offset + 0 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 1 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 2 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 3 * STORSIZE)(\dst), \fixup)
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#if ((defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4)) || !defined(CONFIG_CPU_MICROMIPS))
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EX(LONG_S, \val, (\offset + 4 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 5 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 6 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 7 * STORSIZE)(\dst), \fixup)
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#endif
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#if (!defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4))
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EX(LONG_S, \val, (\offset + 8 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 9 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 10 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 11 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 12 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 13 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 14 * STORSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 15 * STORSIZE)(\dst), \fixup)
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#endif
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.endm
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.set noreorder
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.align 5
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/*
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* Macro to generate the __bzero{,_user} symbol
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* Arguments:
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* mode: LEGACY_MODE or EVA_MODE
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*/
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.macro __BUILD_BZERO mode
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/* Initialize __memset if this is the first time we call this macro */
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.ifnotdef __memset
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.set __memset, 1
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.hidden __memset /* Make sure it does not leak */
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.endif
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sltiu t0, a2, STORSIZE /* very small region? */
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bnez t0, .Lsmall_memset\@
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andi t0, a0, STORMASK /* aligned? */
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#ifdef CONFIG_CPU_MICROMIPS
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move t8, a1 /* used by 'swp' instruction */
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move t9, a1
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#endif
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#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
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beqz t0, 1f
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PTR_SUBU t0, STORSIZE /* alignment in bytes */
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#else
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.set noat
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li AT, STORSIZE
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beqz t0, 1f
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PTR_SUBU t0, AT /* alignment in bytes */
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.set at
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#endif
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R10KCBARRIER(0(ra))
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#ifdef __MIPSEB__
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EX(LONG_S_L, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */
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#else
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EX(LONG_S_R, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */
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#endif
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PTR_SUBU a0, t0 /* long align ptr */
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PTR_ADDU a2, t0 /* correct size */
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1: ori t1, a2, 0x3f /* # of full blocks */
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xori t1, 0x3f
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beqz t1, .Lmemset_partial\@ /* no block to fill */
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andi t0, a2, 0x40-STORSIZE
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PTR_ADDU t1, a0 /* end address */
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.set reorder
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1: PTR_ADDIU a0, 64
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R10KCBARRIER(0(ra))
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f_fill64 a0, -64, FILL64RG, .Lfwd_fixup\@, \mode
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bne t1, a0, 1b
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.set noreorder
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.Lmemset_partial\@:
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R10KCBARRIER(0(ra))
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PTR_LA t1, 2f /* where to start */
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#ifdef CONFIG_CPU_MICROMIPS
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LONG_SRL t7, t0, 1
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#endif
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#if LONGSIZE == 4
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PTR_SUBU t1, FILLPTRG
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#else
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.set noat
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LONG_SRL AT, FILLPTRG, 1
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PTR_SUBU t1, AT
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.set at
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#endif
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jr t1
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PTR_ADDU a0, t0 /* dest ptr */
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.set push
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.set noreorder
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.set nomacro
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/* ... but first do longs ... */
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f_fill64 a0, -64, FILL64RG, .Lpartial_fixup\@, \mode
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2: .set pop
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andi a2, STORMASK /* At most one long to go */
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beqz a2, 1f
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PTR_ADDU a0, a2 /* What's left */
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R10KCBARRIER(0(ra))
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#ifdef __MIPSEB__
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EX(LONG_S_R, a1, -1(a0), .Llast_fixup\@)
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#else
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EX(LONG_S_L, a1, -1(a0), .Llast_fixup\@)
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#endif
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1: jr ra
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move a2, zero
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.Lsmall_memset\@:
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beqz a2, 2f
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PTR_ADDU t1, a0, a2
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1: PTR_ADDIU a0, 1 /* fill bytewise */
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R10KCBARRIER(0(ra))
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bne t1, a0, 1b
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sb a1, -1(a0)
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2: jr ra /* done */
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move a2, zero
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.if __memset == 1
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END(memset)
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.set __memset, 0
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.hidden __memset
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.endif
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.Lfirst_fixup\@:
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jr ra
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nop
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.Lfwd_fixup\@:
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PTR_L t0, TI_TASK($28)
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andi a2, 0x3f
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LONG_L t0, THREAD_BUADDR(t0)
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LONG_ADDU a2, t1
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jr ra
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LONG_SUBU a2, t0
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.Lpartial_fixup\@:
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PTR_L t0, TI_TASK($28)
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andi a2, STORMASK
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LONG_L t0, THREAD_BUADDR(t0)
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LONG_ADDU a2, t1
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jr ra
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LONG_SUBU a2, t0
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.Llast_fixup\@:
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jr ra
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andi v1, a2, STORMASK
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.endm
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/*
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* memset(void *s, int c, size_t n)
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*
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* a0: start of area to clear
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* a1: char to fill with
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* a2: size of area to clear
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*/
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LEAF(memset)
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beqz a1, 1f
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move v0, a0 /* result */
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andi a1, 0xff /* spread fillword */
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LONG_SLL t1, a1, 8
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or a1, t1
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LONG_SLL t1, a1, 16
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#if LONGSIZE == 8
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or a1, t1
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LONG_SLL t1, a1, 32
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#endif
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or a1, t1
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1:
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#ifndef CONFIG_EVA
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FEXPORT(__bzero)
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#endif
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__BUILD_BZERO LEGACY_MODE
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#ifdef CONFIG_EVA
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LEAF(__bzero)
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__BUILD_BZERO EVA_MODE
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END(__bzero)
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#endif
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