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7bdcead7a7
SOUT has many bits and need to be cleared before set new value.
Write only could do the clear, but for MOUT, it clears bits that
should not be cleared. So use a mask to reset only the needed bits.
this fixes HDMI issues on MT7623/BPI-R2 since 5.13
Fixes: 440147639a ("soc: mediatek: mmsys: Use an array for setting the routing registers")
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
Link: https://lore.kernel.org/r/20210729070549.5514-1-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
62 lines
2.0 KiB
C
62 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT8183_MMSYS_H
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#define __SOC_MEDIATEK_MT8183_MMSYS_H
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#define MT8183_DISP_OVL0_MOUT_EN 0xf00
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#define MT8183_DISP_OVL0_2L_MOUT_EN 0xf04
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#define MT8183_DISP_OVL1_2L_MOUT_EN 0xf08
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#define MT8183_DISP_DITHER0_MOUT_EN 0xf0c
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#define MT8183_DISP_PATH0_SEL_IN 0xf24
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#define MT8183_DISP_DSI0_SEL_IN 0xf2c
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#define MT8183_DISP_DPI0_SEL_IN 0xf30
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#define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50
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#define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54
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#define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
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#define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
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#define MT8183_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
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#define MT8183_DITHER0_MOUT_IN_DSI0 BIT(0)
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#define MT8183_DISP_PATH0_SEL_IN_OVL0_2L 0x1
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#define MT8183_DSI0_SEL_IN_RDMA0 0x1
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#define MT8183_DSI0_SEL_IN_RDMA1 0x3
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#define MT8183_DPI0_SEL_IN_RDMA0 0x1
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#define MT8183_DPI0_SEL_IN_RDMA1 0x2
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#define MT8183_RDMA0_SOUT_COLOR0 0x1
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#define MT8183_RDMA1_SOUT_DSI0 0x1
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static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
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{
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DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
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MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L,
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MT8183_OVL0_MOUT_EN_OVL0_2L
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}, {
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DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
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MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0,
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MT8183_OVL0_2L_MOUT_EN_DISP_PATH0
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}, {
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DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1,
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MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
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MT8183_OVL1_2L_MOUT_EN_RDMA1
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}, {
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DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
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MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
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MT8183_DITHER0_MOUT_IN_DSI0
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}, {
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DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
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MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L,
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MT8183_DISP_PATH0_SEL_IN_OVL0_2L
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
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MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1,
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MT8183_DPI0_SEL_IN_RDMA1
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}, {
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
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MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0,
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MT8183_RDMA0_SOUT_COLOR0
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}
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};
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#endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
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