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6f1a1ced9e
Add device tree bindings for graphics clock subsystem clock controller for Qualcomm Technology Inc's SC7280 SoCs. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1626189143-12957-5-git-send-email-tdas@codeaurora.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
36 lines
990 B
C
36 lines
990 B
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SC7280_H
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#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SC7280_H
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/* GPU_CC clocks */
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#define GPU_CC_PLL0 0
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#define GPU_CC_PLL1 1
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#define GPU_CC_AHB_CLK 2
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#define GPU_CC_CB_CLK 3
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#define GPU_CC_CRC_AHB_CLK 4
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#define GPU_CC_CX_GMU_CLK 5
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#define GPU_CC_CX_SNOC_DVM_CLK 6
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#define GPU_CC_CXO_AON_CLK 7
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#define GPU_CC_CXO_CLK 8
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#define GPU_CC_GMU_CLK_SRC 9
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#define GPU_CC_GX_GMU_CLK 10
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#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 11
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#define GPU_CC_HUB_AHB_DIV_CLK_SRC 12
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#define GPU_CC_HUB_AON_CLK 13
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#define GPU_CC_HUB_CLK_SRC 14
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#define GPU_CC_HUB_CX_INT_CLK 15
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#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 16
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#define GPU_CC_MND1X_0_GFX3D_CLK 17
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#define GPU_CC_MND1X_1_GFX3D_CLK 18
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#define GPU_CC_SLEEP_CLK 19
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/* GPU_CC power domains */
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#define GPU_CC_CX_GDSC 0
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#define GPU_CC_GX_GDSC 1
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#endif
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