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a949f2cf1a
System Register is used to configure system behavior, like USI protocol, etc. SYSREG clocks should be provided to corresponding syscon nodes, to make it possible to modify SYSREG registers. While at it, add also missing PMU and GPIO clocks, which looks necessary and might be needed for corresponding Exynos850 features soon. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20211217161549.24836-2-semen.protsenko@linaro.org
192 lines
5.6 KiB
C
192 lines
5.6 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (C) 2021 Linaro Ltd.
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* Author: Sam Protsenko <semen.protsenko@linaro.org>
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*
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* Device Tree binding constants for Exynos850 clock controller.
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*/
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#ifndef _DT_BINDINGS_CLOCK_EXYNOS_850_H
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#define _DT_BINDINGS_CLOCK_EXYNOS_850_H
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/* CMU_TOP */
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#define CLK_FOUT_SHARED0_PLL 1
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#define CLK_FOUT_SHARED1_PLL 2
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#define CLK_FOUT_MMC_PLL 3
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#define CLK_MOUT_SHARED0_PLL 4
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#define CLK_MOUT_SHARED1_PLL 5
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#define CLK_MOUT_MMC_PLL 6
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#define CLK_MOUT_CORE_BUS 7
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#define CLK_MOUT_CORE_CCI 8
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#define CLK_MOUT_CORE_MMC_EMBD 9
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#define CLK_MOUT_CORE_SSS 10
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#define CLK_MOUT_DPU 11
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#define CLK_MOUT_HSI_BUS 12
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#define CLK_MOUT_HSI_MMC_CARD 13
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#define CLK_MOUT_HSI_USB20DRD 14
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#define CLK_MOUT_PERI_BUS 15
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#define CLK_MOUT_PERI_UART 16
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#define CLK_MOUT_PERI_IP 17
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#define CLK_DOUT_SHARED0_DIV3 18
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#define CLK_DOUT_SHARED0_DIV2 19
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#define CLK_DOUT_SHARED1_DIV3 20
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#define CLK_DOUT_SHARED1_DIV2 21
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#define CLK_DOUT_SHARED0_DIV4 22
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#define CLK_DOUT_SHARED1_DIV4 23
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#define CLK_DOUT_CORE_BUS 24
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#define CLK_DOUT_CORE_CCI 25
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#define CLK_DOUT_CORE_MMC_EMBD 26
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#define CLK_DOUT_CORE_SSS 27
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#define CLK_DOUT_DPU 28
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#define CLK_DOUT_HSI_BUS 29
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#define CLK_DOUT_HSI_MMC_CARD 30
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#define CLK_DOUT_HSI_USB20DRD 31
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#define CLK_DOUT_PERI_BUS 32
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#define CLK_DOUT_PERI_UART 33
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#define CLK_DOUT_PERI_IP 34
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#define CLK_GOUT_CORE_BUS 35
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#define CLK_GOUT_CORE_CCI 36
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#define CLK_GOUT_CORE_MMC_EMBD 37
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#define CLK_GOUT_CORE_SSS 38
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#define CLK_GOUT_DPU 39
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#define CLK_GOUT_HSI_BUS 40
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#define CLK_GOUT_HSI_MMC_CARD 41
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#define CLK_GOUT_HSI_USB20DRD 42
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#define CLK_GOUT_PERI_BUS 43
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#define CLK_GOUT_PERI_UART 44
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#define CLK_GOUT_PERI_IP 45
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#define CLK_MOUT_CLKCMU_APM_BUS 46
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#define CLK_DOUT_CLKCMU_APM_BUS 47
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#define CLK_GOUT_CLKCMU_APM_BUS 48
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#define TOP_NR_CLK 49
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/* CMU_APM */
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#define CLK_RCO_I3C_PMIC 1
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#define OSCCLK_RCO_APM 2
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#define CLK_RCO_APM__ALV 3
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#define CLK_DLL_DCO 4
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#define CLK_MOUT_APM_BUS_USER 5
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#define CLK_MOUT_RCO_APM_I3C_USER 6
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#define CLK_MOUT_RCO_APM_USER 7
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#define CLK_MOUT_DLL_USER 8
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#define CLK_MOUT_CLKCMU_CHUB_BUS 9
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#define CLK_MOUT_APM_BUS 10
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#define CLK_MOUT_APM_I3C 11
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#define CLK_DOUT_CLKCMU_CHUB_BUS 12
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#define CLK_DOUT_APM_BUS 13
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#define CLK_DOUT_APM_I3C 14
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#define CLK_GOUT_CLKCMU_CMGP_BUS 15
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#define CLK_GOUT_CLKCMU_CHUB_BUS 16
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#define CLK_GOUT_RTC_PCLK 17
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#define CLK_GOUT_TOP_RTC_PCLK 18
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#define CLK_GOUT_I3C_PCLK 19
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#define CLK_GOUT_I3C_SCLK 20
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#define CLK_GOUT_SPEEDY_PCLK 21
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#define CLK_GOUT_GPIO_ALIVE_PCLK 22
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#define CLK_GOUT_PMU_ALIVE_PCLK 23
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#define CLK_GOUT_SYSREG_APM_PCLK 24
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#define APM_NR_CLK 25
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/* CMU_CMGP */
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#define CLK_RCO_CMGP 1
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#define CLK_MOUT_CMGP_ADC 2
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#define CLK_MOUT_CMGP_USI0 3
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#define CLK_MOUT_CMGP_USI1 4
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#define CLK_DOUT_CMGP_ADC 5
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#define CLK_DOUT_CMGP_USI0 6
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#define CLK_DOUT_CMGP_USI1 7
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#define CLK_GOUT_CMGP_ADC_S0_PCLK 8
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#define CLK_GOUT_CMGP_ADC_S1_PCLK 9
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#define CLK_GOUT_CMGP_GPIO_PCLK 10
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#define CLK_GOUT_CMGP_USI0_IPCLK 11
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#define CLK_GOUT_CMGP_USI0_PCLK 12
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#define CLK_GOUT_CMGP_USI1_IPCLK 13
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#define CLK_GOUT_CMGP_USI1_PCLK 14
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#define CLK_GOUT_SYSREG_CMGP_PCLK 15
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#define CMGP_NR_CLK 16
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/* CMU_HSI */
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#define CLK_MOUT_HSI_BUS_USER 1
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#define CLK_MOUT_HSI_MMC_CARD_USER 2
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#define CLK_MOUT_HSI_USB20DRD_USER 3
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#define CLK_MOUT_HSI_RTC 4
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#define CLK_GOUT_USB_RTC_CLK 5
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#define CLK_GOUT_USB_REF_CLK 6
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#define CLK_GOUT_USB_PHY_REF_CLK 7
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#define CLK_GOUT_USB_PHY_ACLK 8
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#define CLK_GOUT_USB_BUS_EARLY_CLK 9
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#define CLK_GOUT_GPIO_HSI_PCLK 10
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#define CLK_GOUT_MMC_CARD_ACLK 11
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#define CLK_GOUT_MMC_CARD_SDCLKIN 12
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#define CLK_GOUT_SYSREG_HSI_PCLK 13
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#define HSI_NR_CLK 14
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/* CMU_PERI */
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#define CLK_MOUT_PERI_BUS_USER 1
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#define CLK_MOUT_PERI_UART_USER 2
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#define CLK_MOUT_PERI_HSI2C_USER 3
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#define CLK_MOUT_PERI_SPI_USER 4
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#define CLK_DOUT_PERI_HSI2C0 5
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#define CLK_DOUT_PERI_HSI2C1 6
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#define CLK_DOUT_PERI_HSI2C2 7
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#define CLK_DOUT_PERI_SPI0 8
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#define CLK_GOUT_PERI_HSI2C0 9
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#define CLK_GOUT_PERI_HSI2C1 10
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#define CLK_GOUT_PERI_HSI2C2 11
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#define CLK_GOUT_GPIO_PERI_PCLK 12
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#define CLK_GOUT_HSI2C0_IPCLK 13
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#define CLK_GOUT_HSI2C0_PCLK 14
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#define CLK_GOUT_HSI2C1_IPCLK 15
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#define CLK_GOUT_HSI2C1_PCLK 16
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#define CLK_GOUT_HSI2C2_IPCLK 17
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#define CLK_GOUT_HSI2C2_PCLK 18
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#define CLK_GOUT_I2C0_PCLK 19
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#define CLK_GOUT_I2C1_PCLK 20
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#define CLK_GOUT_I2C2_PCLK 21
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#define CLK_GOUT_I2C3_PCLK 22
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#define CLK_GOUT_I2C4_PCLK 23
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#define CLK_GOUT_I2C5_PCLK 24
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#define CLK_GOUT_I2C6_PCLK 25
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#define CLK_GOUT_MCT_PCLK 26
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#define CLK_GOUT_PWM_MOTOR_PCLK 27
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#define CLK_GOUT_SPI0_IPCLK 28
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#define CLK_GOUT_SPI0_PCLK 29
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#define CLK_GOUT_SYSREG_PERI_PCLK 30
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#define CLK_GOUT_UART_IPCLK 31
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#define CLK_GOUT_UART_PCLK 32
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#define CLK_GOUT_WDT0_PCLK 33
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#define CLK_GOUT_WDT1_PCLK 34
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#define PERI_NR_CLK 35
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/* CMU_CORE */
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#define CLK_MOUT_CORE_BUS_USER 1
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#define CLK_MOUT_CORE_CCI_USER 2
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#define CLK_MOUT_CORE_MMC_EMBD_USER 3
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#define CLK_MOUT_CORE_SSS_USER 4
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#define CLK_MOUT_CORE_GIC 5
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#define CLK_DOUT_CORE_BUSP 6
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#define CLK_GOUT_CCI_ACLK 7
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#define CLK_GOUT_GIC_CLK 8
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#define CLK_GOUT_MMC_EMBD_ACLK 9
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#define CLK_GOUT_MMC_EMBD_SDCLKIN 10
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#define CLK_GOUT_SSS_ACLK 11
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#define CLK_GOUT_SSS_PCLK 12
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#define CLK_GOUT_GPIO_CORE_PCLK 13
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#define CLK_GOUT_SYSREG_CORE_PCLK 14
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#define CORE_NR_CLK 15
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/* CMU_DPU */
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#define CLK_MOUT_DPU_USER 1
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#define CLK_DOUT_DPU_BUSP 2
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#define CLK_GOUT_DPU_CMU_DPU_PCLK 3
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#define CLK_GOUT_DPU_DECON0_ACLK 4
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#define CLK_GOUT_DPU_DMA_ACLK 5
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#define CLK_GOUT_DPU_DPP_ACLK 6
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#define CLK_GOUT_DPU_PPMU_ACLK 7
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#define CLK_GOUT_DPU_PPMU_PCLK 8
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#define CLK_GOUT_DPU_SMMU_CLK 9
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#define CLK_GOUT_DPU_SYSREG_PCLK 10
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#define DPU_NR_CLK 11
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS_850_H */
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