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11d73c56b9
ARCH_MULTIPLATFORM. (For multi-platform code it's already unused since387798b
(ARM: initial multiplatform support).) To make this work some code out of arch/arm needed to be adapted. The respective changes got acks by their maintainers to be taken via armsoc (with Andrew Morton substituting for Alessandro Zummo as rtc maintainer). Compared to the previous pull request there was another patch added that fixes a (non-critical) regression on ixp4xx. Olof Johansson asked to not squash this fix into the original commit to save him from the need to reverify the series. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABCAAGBQJTA8PeAAoJEOLc3ZEyZpvW5GEP/iz+HIx8Rkf3exUOorZB0Kef dPC1Bmc4SThffhgmmXTjSapTzjfnuC8xq8dni008L7QR0LFJsC/rw8bR9GqYhTDs EP7Sk0vDJcTUw9dvlIG0jpBioxdsPY7isU8K85tr2a+dzi4JA2h8iv6gE7bsOf1c b18hIWp2ZZdeYQX3OcuzPeVfvXuMaayBJChq0akoW7zqxG2nHG9j1vCSOhBtrgpc xCTuEqPoaDOdXjdhyda//3SKkIYh1eMf+RWMgW38vz2uHEI3AsMn/EWe6pNRKzRt JdVC6LWFl5tl1Dz73NoGFQO+ztTBb2pTrmqggc+Hi4iTekJSmJSFU51D/E0hdJFj KmWDWPLiUdAItjPuRz/HyeZxoIZQjg9PJ8MkjwVNAz4f4Vmw2xNnAV1Eur3k9JyV fo55eaBvy2KIGzBB+/ksMUvs4HzMJ7Z/dVPzZYRF8VxlYFJXExT0O42oeJ8KsfH7 dJ1bjk+3VIWPLH3DHyyiIfBL1oxe4MemqrAREFnN2QxYHyCipXLwH35uNZXAqvcU jverroWnCdrpOn9KI+vpnp/kuE7Qc1IH/AwAZngPj2xhaFapiH6h1JK/xWcWjijR AKv1DhFJMqSp9fvclr/ZAb7o35V/LG0rpCs+oZumCCARwpxkbo8xXgG0CfPsYFrG KwLWPz5zwySGwvDZ2wub =g6PN -----END PGP SIGNATURE----- Merge tag 'dropmachtimexh-v2' of git://git.pengutronix.de/git/ukl/linux into next/cleanup This cleanup series gets rid of <mach/timex.h> for platforms not using ARCH_MULTIPLATFORM. (For multi-platform code it's already unused since387798b
(ARM: initial multiplatform support).) To make this work some code out of arch/arm needed to be adapted. The respective changes got acks by their maintainers to be taken via armsoc (with Andrew Morton substituting for Alessandro Zummo as rtc maintainer). Compared to the previous pull request there was another patch added that fixes a (non-critical) regression on ixp4xx. Olof Johansson asked to not squash this fix into the original commit to save him from the need to reverify the series. * tag 'dropmachtimexh-v2' of git://git.pengutronix.de/git/ukl/linux: ARM: ixp4xx: fix timer latch calculation ARM: drop <mach/timex.h> for !ARCH_MULTIPLATFORM, too ARM: rpc: stop using <mach/timex.h> ARM: ixp4xx: stop using <mach/timex.h> input: ixp4xx-beeper: don't use symbols from <mach/timex.h> ARM: at91: don't use <mach/timex.h> ARM: ep93xx: stop using mach/timex.h ARM: mmp: stop using mach/timex.h ARM: netx: stop using mach/timex.h ARM: sa1100: stop using mach/timex.h clocksource: sirf/marco+prima2: drop usage of CLOCK_TICK_RATE rtc: pxa: drop unused #define TIMER_FREQ rtc: at91sam9: include <mach/hardware.h> explicitly ARM/serial: at91: switch atmel serial to use gpiolib Signed-off-by: Olof Johansson <olof@lixom.net>
275 lines
6.7 KiB
C
275 lines
6.7 KiB
C
/*
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* linux/arch/arm/mach-at91/at91rm9200_time.c
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*
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* Copyright (C) 2003 SAN People
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* Copyright (C) 2003 ATMEL
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/clockchips.h>
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#include <linux/export.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/mach/time.h>
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#include <mach/at91_st.h>
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#include <mach/hardware.h>
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static unsigned long last_crtr;
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static u32 irqmask;
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static struct clock_event_device clkevt;
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#define RM9200_TIMER_LATCH ((AT91_SLOW_CLOCK + HZ/2) / HZ)
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/*
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* The ST_CRTR is updated asynchronously to the master clock ... but
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* the updates as seen by the CPU don't seem to be strictly monotonic.
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* Waiting until we read the same value twice avoids glitching.
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*/
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static inline unsigned long read_CRTR(void)
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{
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unsigned long x1, x2;
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x1 = at91_st_read(AT91_ST_CRTR);
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do {
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x2 = at91_st_read(AT91_ST_CRTR);
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if (x1 == x2)
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break;
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x1 = x2;
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} while (1);
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return x1;
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}
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/*
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* IRQ handler for the timer.
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*/
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static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
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{
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u32 sr = at91_st_read(AT91_ST_SR) & irqmask;
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/*
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* irqs should be disabled here, but as the irq is shared they are only
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* guaranteed to be off if the timer irq is registered first.
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*/
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WARN_ON_ONCE(!irqs_disabled());
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/* simulate "oneshot" timer with alarm */
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if (sr & AT91_ST_ALMS) {
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clkevt.event_handler(&clkevt);
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return IRQ_HANDLED;
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}
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/* periodic mode should handle delayed ticks */
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if (sr & AT91_ST_PITS) {
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u32 crtr = read_CRTR();
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while (((crtr - last_crtr) & AT91_ST_CRTV) >= RM9200_TIMER_LATCH) {
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last_crtr += RM9200_TIMER_LATCH;
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clkevt.event_handler(&clkevt);
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}
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return IRQ_HANDLED;
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}
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/* this irq is shared ... */
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return IRQ_NONE;
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}
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static struct irqaction at91rm9200_timer_irq = {
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.name = "at91_tick",
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.flags = IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = at91rm9200_timer_interrupt,
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.irq = NR_IRQS_LEGACY + AT91_ID_SYS,
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};
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static cycle_t read_clk32k(struct clocksource *cs)
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{
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return read_CRTR();
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}
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static struct clocksource clk32k = {
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.name = "32k_counter",
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.rating = 150,
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.read = read_clk32k,
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.mask = CLOCKSOURCE_MASK(20),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static void
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clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
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{
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/* Disable and flush pending timer interrupts */
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at91_st_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
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at91_st_read(AT91_ST_SR);
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last_crtr = read_CRTR();
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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/* PIT for periodic irqs; fixed rate of 1/HZ */
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irqmask = AT91_ST_PITS;
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at91_st_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* ALM for oneshot irqs, set by next_event()
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* before 32 seconds have passed
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*/
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irqmask = AT91_ST_ALMS;
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at91_st_write(AT91_ST_RTAR, last_crtr);
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_RESUME:
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irqmask = 0;
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break;
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}
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at91_st_write(AT91_ST_IER, irqmask);
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}
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static int
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clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
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{
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u32 alm;
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int status = 0;
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BUG_ON(delta < 2);
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/* The alarm IRQ uses absolute time (now+delta), not the relative
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* time (delta) in our calling convention. Like all clockevents
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* using such "match" hardware, we have a race to defend against.
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*
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* Our defense here is to have set up the clockevent device so the
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* delta is at least two. That way we never end up writing RTAR
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* with the value then held in CRTR ... which would mean the match
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* wouldn't trigger until 32 seconds later, after CRTR wraps.
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*/
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alm = read_CRTR();
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/* Cancel any pending alarm; flush any pending IRQ */
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at91_st_write(AT91_ST_RTAR, alm);
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at91_st_read(AT91_ST_SR);
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/* Schedule alarm by writing RTAR. */
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alm += delta;
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at91_st_write(AT91_ST_RTAR, alm);
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return status;
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}
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static struct clock_event_device clkevt = {
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.name = "at91_tick",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.rating = 150,
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.set_next_event = clkevt32k_next_event,
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.set_mode = clkevt32k_mode,
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};
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void __iomem *at91_st_base;
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EXPORT_SYMBOL_GPL(at91_st_base);
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#ifdef CONFIG_OF
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static struct of_device_id at91rm9200_st_timer_ids[] = {
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{ .compatible = "atmel,at91rm9200-st" },
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{ /* sentinel */ }
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};
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static int __init of_at91rm9200_st_init(void)
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{
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struct device_node *np;
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int ret;
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np = of_find_matching_node(NULL, at91rm9200_st_timer_ids);
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if (!np)
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goto err;
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at91_st_base = of_iomap(np, 0);
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if (!at91_st_base)
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goto node_err;
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/* Get the interrupts property */
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ret = irq_of_parse_and_map(np, 0);
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if (!ret)
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goto ioremap_err;
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at91rm9200_timer_irq.irq = ret;
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of_node_put(np);
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return 0;
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ioremap_err:
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iounmap(at91_st_base);
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node_err:
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of_node_put(np);
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err:
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return -EINVAL;
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}
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#else
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static int __init of_at91rm9200_st_init(void)
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{
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return -EINVAL;
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}
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#endif
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void __init at91rm9200_ioremap_st(u32 addr)
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{
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#ifdef CONFIG_OF
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struct device_node *np;
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np = of_find_matching_node(NULL, at91rm9200_st_timer_ids);
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if (np) {
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of_node_put(np);
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return;
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}
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#endif
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at91_st_base = ioremap(addr, 256);
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if (!at91_st_base)
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panic("Impossible to ioremap ST\n");
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}
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/*
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* ST (system timer) module supports both clockevents and clocksource.
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*/
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void __init at91rm9200_timer_init(void)
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{
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/* For device tree enabled device: initialize here */
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of_at91rm9200_st_init();
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/* Disable all timer interrupts, and clear any pending ones */
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at91_st_write(AT91_ST_IDR,
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AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
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at91_st_read(AT91_ST_SR);
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/* Make IRQs happen for the system timer */
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setup_irq(at91rm9200_timer_irq.irq, &at91rm9200_timer_irq);
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/* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
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* directly for the clocksource and all clockevents, after adjusting
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* its prescaler from the 1 Hz default.
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*/
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at91_st_write(AT91_ST_RTMR, 1);
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/* Setup timer clockevent, with minimum of two ticks (important!!) */
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clkevt.cpumask = cpumask_of(0);
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clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK,
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2, AT91_ST_ALMV);
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/* register clocksource */
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clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
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}
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