mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-23 11:04:44 +08:00
18589d74f4
UAPI Changes: - Not necessarily one, but we document that userspace needs to force probe connectors. Cross-subsystem Changes: - Require FB_ATY_CT for aty on sparc64. - video: Fix documentation, and a few compiler warnings. - Add devicetree bindings for DP connectors. - dma-buf: Update kernel-doc, and add might_lock for resv objects in begin/end_cpu_access. Core Changes: - ttm: Warn when releasing a pinned bo. - ttm: Cleanup bo size handling. - cma-helper: Remove prime infix, and implement mmap as GEM CMA functions. - Split drm_prime_sg_to_page_addr_arrays into 2 functions. - Add a new api to install irq using devm. - Update panel kerneldoc to inline style. - Add DP support to drm/bridge. - Assorted small fixes to ttm, fb-helper, scheduler. - Add atomic_commit_setup function callback. - Automatically use the atomic gamma_set, instead of forcing drivers to declare the default atomic version. - Allow using degamma for legacy gamma if gamma is not available. - Clarify that primary/cursor planes are not tied to 1 crtc (depending on possible_crtcs). - ttm: Cleanup the lru handler. Driver Changes: - Add pm support to ingenic. - Assorted small fixes in radeon, via, rockchip, omap2fb, kmb, gma500, nouveau, virtio, hisilicon, ingenic, s6e63m0 panel, ast, udlfb. - Add BOE NV110WTM-N61, ys57pss36bh5gq, Khadas TS050 panels. - Stop using pages with drm_prime_sg_to_page_addr_arrays, and switch all callers to use ttm_sg_tt_init. - Cleanup compiler and docbook warnings in a lot of fbdev devices. - Use the drmm_vram_helper in hisilicon. - Add support for BCM2711 DSI1 in vc4. - Add support for 8-bit delta RGB panels to ingenic. - Add documentation on how to test vkms. - Convert vc4 to atomic helpers. - Use degamma instead of gamma table in omap, to add support for CTM and color encoding/range properties. - Rework omap DSI code, and merge all omapdrm modules now that the last omap panel is now a drm panel. - More refactoring of omap dsi code. - Enable 10/12 bpc outputs in vc4. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEuXvWqAysSYEJGuVH/lWMcqZwE8MFAl/bLtAACgkQ/lWMcqZw E8M5mBAAs6iA3giF+LrzQzszZqOFmtExwjHsvJXDtiINrVubdRov2XbbaOZ+8Eax Cnnc5QzokJV8v1IReImz+cP7i4uXyWmwQsthY2WvHYLXZmZfZUV+rK4cCtJIKXlR 9EvkEFtdPZ6OpyJ8p1G0r/UNqXxqOl4pEhp6NZdSj1mscz2yux/BuqX+1tX1j5+G SIfwcKIY+nIwnVpKwhJplJNfFwthRzENxq2KMt+PGLcpOWLHEgwqzKoR+ddTcKf2 Nk1w2OERbnBVRt8NzCIeyczlSp4QuB+NpE5mFEBedmLatGYqwAIwPMt22AVRP9rc SdXqjVxg3UJ5UNMYXQwjrnJq1nIm1ViYt7za/e2aMC8g9oI7tNQ5uI7XViO6+tk5 3vQV40pHVfMLGzkzqGhv9qHYAkkc+gPMAXwObuzmYppVVZn8dnrkAco7Ib8WPrRc g8JD0bpIsOrgqCTj2W54fC/ZP7hQZpffOrxWY7alhlriEl4E7To6OvTwEavIzxCm ajkO129oItOcATDTGiUV3JRWCTdCj4cNz7cQi4pC2QgaUIy8twjm57V8nnFDUCNg ifi1dIY24DOrHxdmZ8sAWZRoPzcl5a84c8EqEkGZieEsdr3Za4XMZD8tqI2uSJrU x+OfqgfvqNZenkuc+SUDZJQ855iqdkzJcqZnkAn61VpPh7XCtxk= =orEC -----END PGP SIGNATURE----- Merge tag 'drm-misc-next-2020-12-17' of git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for v5.12: UAPI Changes: - Not necessarily one, but we document that userspace needs to force probe connectors. Cross-subsystem Changes: - Require FB_ATY_CT for aty on sparc64. - video: Fix documentation, and a few compiler warnings. - Add devicetree bindings for DP connectors. - dma-buf: Update kernel-doc, and add might_lock for resv objects in begin/end_cpu_access. Core Changes: - ttm: Warn when releasing a pinned bo. - ttm: Cleanup bo size handling. - cma-helper: Remove prime infix, and implement mmap as GEM CMA functions. - Split drm_prime_sg_to_page_addr_arrays into 2 functions. - Add a new api to install irq using devm. - Update panel kerneldoc to inline style. - Add DP support to drm/bridge. - Assorted small fixes to ttm, fb-helper, scheduler. - Add atomic_commit_setup function callback. - Automatically use the atomic gamma_set, instead of forcing drivers to declare the default atomic version. - Allow using degamma for legacy gamma if gamma is not available. - Clarify that primary/cursor planes are not tied to 1 crtc (depending on possible_crtcs). - ttm: Cleanup the lru handler. Driver Changes: - Add pm support to ingenic. - Assorted small fixes in radeon, via, rockchip, omap2fb, kmb, gma500, nouveau, virtio, hisilicon, ingenic, s6e63m0 panel, ast, udlfb. - Add BOE NV110WTM-N61, ys57pss36bh5gq, Khadas TS050 panels. - Stop using pages with drm_prime_sg_to_page_addr_arrays, and switch all callers to use ttm_sg_tt_init. - Cleanup compiler and docbook warnings in a lot of fbdev devices. - Use the drmm_vram_helper in hisilicon. - Add support for BCM2711 DSI1 in vc4. - Add support for 8-bit delta RGB panels to ingenic. - Add documentation on how to test vkms. - Convert vc4 to atomic helpers. - Use degamma instead of gamma table in omap, to add support for CTM and color encoding/range properties. - Rework omap DSI code, and merge all omapdrm modules now that the last omap panel is now a drm panel. - More refactoring of omap dsi code. - Enable 10/12 bpc outputs in vc4. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/78381a4f-45fd-aed4-174a-94ba051edd37@linux.intel.com
1312 lines
32 KiB
C
1312 lines
32 KiB
C
/*
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* Copyright 2007 Dave Airlied
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/*
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* Authors: Dave Airlied <airlied@linux.ie>
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* Ben Skeggs <darktama@iinet.net.au>
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* Jeremy Kolb <jkolb@brandeis.edu>
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*/
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#include <linux/dma-mapping.h>
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#include "nouveau_drv.h"
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#include "nouveau_chan.h"
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#include "nouveau_fence.h"
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#include "nouveau_bo.h"
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#include "nouveau_ttm.h"
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#include "nouveau_gem.h"
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#include "nouveau_mem.h"
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#include "nouveau_vmm.h"
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#include <nvif/class.h>
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#include <nvif/if500b.h>
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#include <nvif/if900b.h>
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static int nouveau_ttm_tt_bind(struct ttm_bo_device *bdev, struct ttm_tt *ttm,
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struct ttm_resource *reg);
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static void nouveau_ttm_tt_unbind(struct ttm_bo_device *bdev, struct ttm_tt *ttm);
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/*
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* NV10-NV40 tiling helpers
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*/
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static void
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nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
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u32 addr, u32 size, u32 pitch, u32 flags)
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{
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struct nouveau_drm *drm = nouveau_drm(dev);
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int i = reg - drm->tile.reg;
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struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
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struct nvkm_fb_tile *tile = &fb->tile.region[i];
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nouveau_fence_unref(®->fence);
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if (tile->pitch)
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nvkm_fb_tile_fini(fb, i, tile);
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if (pitch)
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nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
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nvkm_fb_tile_prog(fb, i, tile);
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}
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static struct nouveau_drm_tile *
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nv10_bo_get_tile_region(struct drm_device *dev, int i)
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{
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct nouveau_drm_tile *tile = &drm->tile.reg[i];
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spin_lock(&drm->tile.lock);
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if (!tile->used &&
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(!tile->fence || nouveau_fence_done(tile->fence)))
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tile->used = true;
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else
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tile = NULL;
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spin_unlock(&drm->tile.lock);
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return tile;
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}
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static void
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nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
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struct dma_fence *fence)
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{
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struct nouveau_drm *drm = nouveau_drm(dev);
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if (tile) {
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spin_lock(&drm->tile.lock);
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tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
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tile->used = false;
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spin_unlock(&drm->tile.lock);
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}
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}
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static struct nouveau_drm_tile *
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nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
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u32 size, u32 pitch, u32 zeta)
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{
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
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struct nouveau_drm_tile *tile, *found = NULL;
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int i;
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for (i = 0; i < fb->tile.regions; i++) {
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tile = nv10_bo_get_tile_region(dev, i);
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if (pitch && !found) {
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found = tile;
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continue;
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} else if (tile && fb->tile.region[i].pitch) {
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/* Kill an unused tile region. */
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nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
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}
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nv10_bo_put_tile_region(dev, tile, NULL);
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}
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if (found)
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nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta);
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return found;
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}
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static void
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nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
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{
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struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
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struct drm_device *dev = drm->dev;
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struct nouveau_bo *nvbo = nouveau_bo(bo);
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WARN_ON(nvbo->bo.pin_count > 0);
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nouveau_bo_del_io_reserve_lru(bo);
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nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
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/*
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* If nouveau_bo_new() allocated this buffer, the GEM object was never
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* initialized, so don't attempt to release it.
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*/
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if (bo->base.dev)
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drm_gem_object_release(&bo->base);
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kfree(nvbo);
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}
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static inline u64
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roundup_64(u64 x, u32 y)
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{
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x += y - 1;
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do_div(x, y);
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return x * y;
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}
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static void
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nouveau_bo_fixup_align(struct nouveau_bo *nvbo, int *align, u64 *size)
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{
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struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
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struct nvif_device *device = &drm->client.device;
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if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
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if (nvbo->mode) {
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if (device->info.chipset >= 0x40) {
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*align = 65536;
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*size = roundup_64(*size, 64 * nvbo->mode);
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} else if (device->info.chipset >= 0x30) {
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*align = 32768;
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*size = roundup_64(*size, 64 * nvbo->mode);
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} else if (device->info.chipset >= 0x20) {
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*align = 16384;
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*size = roundup_64(*size, 64 * nvbo->mode);
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} else if (device->info.chipset >= 0x10) {
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*align = 16384;
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*size = roundup_64(*size, 32 * nvbo->mode);
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}
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}
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} else {
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*size = roundup_64(*size, (1 << nvbo->page));
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*align = max((1 << nvbo->page), *align);
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}
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*size = roundup_64(*size, PAGE_SIZE);
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}
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struct nouveau_bo *
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nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain,
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u32 tile_mode, u32 tile_flags)
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{
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struct nouveau_drm *drm = cli->drm;
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struct nouveau_bo *nvbo;
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struct nvif_mmu *mmu = &cli->mmu;
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struct nvif_vmm *vmm = cli->svm.cli ? &cli->svm.vmm : &cli->vmm.vmm;
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int i, pi = -1;
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if (!*size) {
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NV_WARN(drm, "skipped size %016llx\n", *size);
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return ERR_PTR(-EINVAL);
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}
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nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
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if (!nvbo)
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return ERR_PTR(-ENOMEM);
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INIT_LIST_HEAD(&nvbo->head);
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INIT_LIST_HEAD(&nvbo->entry);
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INIT_LIST_HEAD(&nvbo->vma_list);
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nvbo->bo.bdev = &drm->ttm.bdev;
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/* This is confusing, and doesn't actually mean we want an uncached
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* mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
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* into in nouveau_gem_new().
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*/
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if (domain & NOUVEAU_GEM_DOMAIN_COHERENT) {
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/* Determine if we can get a cache-coherent map, forcing
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* uncached mapping if we can't.
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*/
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if (!nouveau_drm_use_coherent_gpu_mapping(drm))
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nvbo->force_coherent = true;
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}
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if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) {
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nvbo->kind = (tile_flags & 0x0000ff00) >> 8;
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if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
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kfree(nvbo);
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return ERR_PTR(-EINVAL);
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}
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nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind;
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} else
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if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
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nvbo->kind = (tile_flags & 0x00007f00) >> 8;
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nvbo->comp = (tile_flags & 0x00030000) >> 16;
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if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
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kfree(nvbo);
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return ERR_PTR(-EINVAL);
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}
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} else {
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nvbo->zeta = (tile_flags & 0x00000007);
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}
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nvbo->mode = tile_mode;
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nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG);
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/* Determine the desirable target GPU page size for the buffer. */
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for (i = 0; i < vmm->page_nr; i++) {
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/* Because we cannot currently allow VMM maps to fail
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* during buffer migration, we need to determine page
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* size for the buffer up-front, and pre-allocate its
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* page tables.
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*
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* Skip page sizes that can't support needed domains.
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*/
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if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE &&
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(domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram)
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continue;
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if ((domain & NOUVEAU_GEM_DOMAIN_GART) &&
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(!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
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continue;
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/* Select this page size if it's the first that supports
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* the potential memory domains, or when it's compatible
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* with the requested compression settings.
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*/
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if (pi < 0 || !nvbo->comp || vmm->page[i].comp)
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pi = i;
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/* Stop once the buffer is larger than the current page size. */
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if (*size >= 1ULL << vmm->page[i].shift)
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break;
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}
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if (WARN_ON(pi < 0))
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return ERR_PTR(-EINVAL);
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/* Disable compression if suitable settings couldn't be found. */
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if (nvbo->comp && !vmm->page[pi].comp) {
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if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100)
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nvbo->kind = mmu->kind[nvbo->kind];
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nvbo->comp = 0;
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}
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nvbo->page = vmm->page[pi].shift;
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nouveau_bo_fixup_align(nvbo, align, size);
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return nvbo;
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}
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int
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nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 domain,
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struct sg_table *sg, struct dma_resv *robj)
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{
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int type = sg ? ttm_bo_type_sg : ttm_bo_type_device;
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size_t acc_size;
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int ret;
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acc_size = ttm_bo_dma_acc_size(nvbo->bo.bdev, size, sizeof(*nvbo));
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nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
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nouveau_bo_placement_set(nvbo, domain, 0);
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INIT_LIST_HEAD(&nvbo->io_reserve_lru);
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ret = ttm_bo_init(nvbo->bo.bdev, &nvbo->bo, size, type,
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&nvbo->placement, align >> PAGE_SHIFT, false,
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acc_size, sg, robj, nouveau_bo_del_ttm);
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if (ret) {
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/* ttm will call nouveau_bo_del_ttm if it fails.. */
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return ret;
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}
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return 0;
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}
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int
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nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
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uint32_t domain, uint32_t tile_mode, uint32_t tile_flags,
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struct sg_table *sg, struct dma_resv *robj,
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struct nouveau_bo **pnvbo)
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{
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struct nouveau_bo *nvbo;
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int ret;
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nvbo = nouveau_bo_alloc(cli, &size, &align, domain, tile_mode,
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tile_flags);
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if (IS_ERR(nvbo))
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return PTR_ERR(nvbo);
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ret = nouveau_bo_init(nvbo, size, align, domain, sg, robj);
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if (ret)
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return ret;
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*pnvbo = nvbo;
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return 0;
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}
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static void
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set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t domain)
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{
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*n = 0;
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if (domain & NOUVEAU_GEM_DOMAIN_VRAM) {
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pl[*n].mem_type = TTM_PL_VRAM;
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pl[*n].flags = 0;
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(*n)++;
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}
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if (domain & NOUVEAU_GEM_DOMAIN_GART) {
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pl[*n].mem_type = TTM_PL_TT;
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pl[*n].flags = 0;
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(*n)++;
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}
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if (domain & NOUVEAU_GEM_DOMAIN_CPU) {
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pl[*n].mem_type = TTM_PL_SYSTEM;
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pl[(*n)++].flags = 0;
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}
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}
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static void
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set_placement_range(struct nouveau_bo *nvbo, uint32_t domain)
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{
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struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
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u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT;
|
|
unsigned i, fpfn, lpfn;
|
|
|
|
if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
|
|
nvbo->mode && (domain & NOUVEAU_GEM_DOMAIN_VRAM) &&
|
|
nvbo->bo.mem.num_pages < vram_pages / 4) {
|
|
/*
|
|
* Make sure that the color and depth buffers are handled
|
|
* by independent memory controller units. Up to a 9x
|
|
* speed up when alpha-blending and depth-test are enabled
|
|
* at the same time.
|
|
*/
|
|
if (nvbo->zeta) {
|
|
fpfn = vram_pages / 2;
|
|
lpfn = ~0;
|
|
} else {
|
|
fpfn = 0;
|
|
lpfn = vram_pages / 2;
|
|
}
|
|
for (i = 0; i < nvbo->placement.num_placement; ++i) {
|
|
nvbo->placements[i].fpfn = fpfn;
|
|
nvbo->placements[i].lpfn = lpfn;
|
|
}
|
|
for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
|
|
nvbo->busy_placements[i].fpfn = fpfn;
|
|
nvbo->busy_placements[i].lpfn = lpfn;
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t domain,
|
|
uint32_t busy)
|
|
{
|
|
struct ttm_placement *pl = &nvbo->placement;
|
|
|
|
pl->placement = nvbo->placements;
|
|
set_placement_list(nvbo->placements, &pl->num_placement, domain);
|
|
|
|
pl->busy_placement = nvbo->busy_placements;
|
|
set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
|
|
domain | busy);
|
|
|
|
set_placement_range(nvbo, domain);
|
|
}
|
|
|
|
int
|
|
nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, bool contig)
|
|
{
|
|
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
|
|
struct ttm_buffer_object *bo = &nvbo->bo;
|
|
bool force = false, evict = false;
|
|
int ret;
|
|
|
|
ret = ttm_bo_reserve(bo, false, false, NULL);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
|
|
domain == NOUVEAU_GEM_DOMAIN_VRAM && contig) {
|
|
if (!nvbo->contig) {
|
|
nvbo->contig = true;
|
|
force = true;
|
|
evict = true;
|
|
}
|
|
}
|
|
|
|
if (nvbo->bo.pin_count) {
|
|
bool error = evict;
|
|
|
|
switch (bo->mem.mem_type) {
|
|
case TTM_PL_VRAM:
|
|
error |= !(domain & NOUVEAU_GEM_DOMAIN_VRAM);
|
|
break;
|
|
case TTM_PL_TT:
|
|
error |= !(domain & NOUVEAU_GEM_DOMAIN_GART);
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (error) {
|
|
NV_ERROR(drm, "bo %p pinned elsewhere: "
|
|
"0x%08x vs 0x%08x\n", bo,
|
|
bo->mem.mem_type, domain);
|
|
ret = -EBUSY;
|
|
}
|
|
ttm_bo_pin(&nvbo->bo);
|
|
goto out;
|
|
}
|
|
|
|
if (evict) {
|
|
nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
|
|
ret = nouveau_bo_validate(nvbo, false, false);
|
|
if (ret)
|
|
goto out;
|
|
}
|
|
|
|
nouveau_bo_placement_set(nvbo, domain, 0);
|
|
ret = nouveau_bo_validate(nvbo, false, false);
|
|
if (ret)
|
|
goto out;
|
|
|
|
ttm_bo_pin(&nvbo->bo);
|
|
|
|
switch (bo->mem.mem_type) {
|
|
case TTM_PL_VRAM:
|
|
drm->gem.vram_available -= bo->base.size;
|
|
break;
|
|
case TTM_PL_TT:
|
|
drm->gem.gart_available -= bo->base.size;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
out:
|
|
if (force && ret)
|
|
nvbo->contig = false;
|
|
ttm_bo_unreserve(bo);
|
|
return ret;
|
|
}
|
|
|
|
int
|
|
nouveau_bo_unpin(struct nouveau_bo *nvbo)
|
|
{
|
|
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
|
|
struct ttm_buffer_object *bo = &nvbo->bo;
|
|
int ret;
|
|
|
|
ret = ttm_bo_reserve(bo, false, false, NULL);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ttm_bo_unpin(&nvbo->bo);
|
|
if (!nvbo->bo.pin_count) {
|
|
switch (bo->mem.mem_type) {
|
|
case TTM_PL_VRAM:
|
|
drm->gem.vram_available += bo->base.size;
|
|
break;
|
|
case TTM_PL_TT:
|
|
drm->gem.gart_available += bo->base.size;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
ttm_bo_unreserve(bo);
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
nouveau_bo_map(struct nouveau_bo *nvbo)
|
|
{
|
|
int ret;
|
|
|
|
ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
|
|
|
|
ttm_bo_unreserve(&nvbo->bo);
|
|
return ret;
|
|
}
|
|
|
|
void
|
|
nouveau_bo_unmap(struct nouveau_bo *nvbo)
|
|
{
|
|
if (!nvbo)
|
|
return;
|
|
|
|
ttm_bo_kunmap(&nvbo->kmap);
|
|
}
|
|
|
|
void
|
|
nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
|
|
{
|
|
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
|
|
struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
|
|
int i;
|
|
|
|
if (!ttm_dma)
|
|
return;
|
|
|
|
/* Don't waste time looping if the object is coherent */
|
|
if (nvbo->force_coherent)
|
|
return;
|
|
|
|
for (i = 0; i < ttm_dma->num_pages; i++)
|
|
dma_sync_single_for_device(drm->dev->dev,
|
|
ttm_dma->dma_address[i],
|
|
PAGE_SIZE, DMA_TO_DEVICE);
|
|
}
|
|
|
|
void
|
|
nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
|
|
{
|
|
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
|
|
struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
|
|
int i;
|
|
|
|
if (!ttm_dma)
|
|
return;
|
|
|
|
/* Don't waste time looping if the object is coherent */
|
|
if (nvbo->force_coherent)
|
|
return;
|
|
|
|
for (i = 0; i < ttm_dma->num_pages; i++)
|
|
dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i],
|
|
PAGE_SIZE, DMA_FROM_DEVICE);
|
|
}
|
|
|
|
void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo)
|
|
{
|
|
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
|
|
struct nouveau_bo *nvbo = nouveau_bo(bo);
|
|
|
|
mutex_lock(&drm->ttm.io_reserve_mutex);
|
|
list_move_tail(&nvbo->io_reserve_lru, &drm->ttm.io_reserve_lru);
|
|
mutex_unlock(&drm->ttm.io_reserve_mutex);
|
|
}
|
|
|
|
void nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object *bo)
|
|
{
|
|
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
|
|
struct nouveau_bo *nvbo = nouveau_bo(bo);
|
|
|
|
mutex_lock(&drm->ttm.io_reserve_mutex);
|
|
list_del_init(&nvbo->io_reserve_lru);
|
|
mutex_unlock(&drm->ttm.io_reserve_mutex);
|
|
}
|
|
|
|
int
|
|
nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
|
|
bool no_wait_gpu)
|
|
{
|
|
struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
|
|
int ret;
|
|
|
|
ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx);
|
|
if (ret)
|
|
return ret;
|
|
|
|
nouveau_bo_sync_for_device(nvbo);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
|
|
{
|
|
bool is_iomem;
|
|
u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
|
|
|
|
mem += index;
|
|
|
|
if (is_iomem)
|
|
iowrite16_native(val, (void __force __iomem *)mem);
|
|
else
|
|
*mem = val;
|
|
}
|
|
|
|
u32
|
|
nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
|
|
{
|
|
bool is_iomem;
|
|
u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
|
|
|
|
mem += index;
|
|
|
|
if (is_iomem)
|
|
return ioread32_native((void __force __iomem *)mem);
|
|
else
|
|
return *mem;
|
|
}
|
|
|
|
void
|
|
nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
|
|
{
|
|
bool is_iomem;
|
|
u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
|
|
|
|
mem += index;
|
|
|
|
if (is_iomem)
|
|
iowrite32_native(val, (void __force __iomem *)mem);
|
|
else
|
|
*mem = val;
|
|
}
|
|
|
|
static struct ttm_tt *
|
|
nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags)
|
|
{
|
|
#if IS_ENABLED(CONFIG_AGP)
|
|
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
|
|
|
|
if (drm->agp.bridge) {
|
|
return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags);
|
|
}
|
|
#endif
|
|
|
|
return nouveau_sgdma_create_ttm(bo, page_flags);
|
|
}
|
|
|
|
static int
|
|
nouveau_ttm_tt_bind(struct ttm_bo_device *bdev, struct ttm_tt *ttm,
|
|
struct ttm_resource *reg)
|
|
{
|
|
#if IS_ENABLED(CONFIG_AGP)
|
|
struct nouveau_drm *drm = nouveau_bdev(bdev);
|
|
#endif
|
|
if (!reg)
|
|
return -EINVAL;
|
|
#if IS_ENABLED(CONFIG_AGP)
|
|
if (drm->agp.bridge)
|
|
return ttm_agp_bind(ttm, reg);
|
|
#endif
|
|
return nouveau_sgdma_bind(bdev, ttm, reg);
|
|
}
|
|
|
|
static void
|
|
nouveau_ttm_tt_unbind(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
|
|
{
|
|
#if IS_ENABLED(CONFIG_AGP)
|
|
struct nouveau_drm *drm = nouveau_bdev(bdev);
|
|
|
|
if (drm->agp.bridge) {
|
|
ttm_agp_unbind(ttm);
|
|
return;
|
|
}
|
|
#endif
|
|
nouveau_sgdma_unbind(bdev, ttm);
|
|
}
|
|
|
|
static void
|
|
nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
|
|
{
|
|
struct nouveau_bo *nvbo = nouveau_bo(bo);
|
|
|
|
switch (bo->mem.mem_type) {
|
|
case TTM_PL_VRAM:
|
|
nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART,
|
|
NOUVEAU_GEM_DOMAIN_CPU);
|
|
break;
|
|
default:
|
|
nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_CPU, 0);
|
|
break;
|
|
}
|
|
|
|
*pl = nvbo->placement;
|
|
}
|
|
|
|
static int
|
|
nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
|
|
struct ttm_resource *reg)
|
|
{
|
|
struct nouveau_mem *old_mem = nouveau_mem(&bo->mem);
|
|
struct nouveau_mem *new_mem = nouveau_mem(reg);
|
|
struct nvif_vmm *vmm = &drm->client.vmm.vmm;
|
|
int ret;
|
|
|
|
ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0,
|
|
old_mem->mem.size, &old_mem->vma[0]);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0,
|
|
new_mem->mem.size, &old_mem->vma[1]);
|
|
if (ret)
|
|
goto done;
|
|
|
|
ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]);
|
|
if (ret)
|
|
goto done;
|
|
|
|
ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]);
|
|
done:
|
|
if (ret) {
|
|
nvif_vmm_put(vmm, &old_mem->vma[1]);
|
|
nvif_vmm_put(vmm, &old_mem->vma[0]);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict,
|
|
struct ttm_operation_ctx *ctx,
|
|
struct ttm_resource *new_reg)
|
|
{
|
|
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
|
|
struct nouveau_channel *chan = drm->ttm.chan;
|
|
struct nouveau_cli *cli = (void *)chan->user.client;
|
|
struct nouveau_fence *fence;
|
|
int ret;
|
|
|
|
/* create temporary vmas for the transfer and attach them to the
|
|
* old nvkm_mem node, these will get cleaned up after ttm has
|
|
* destroyed the ttm_resource
|
|
*/
|
|
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
|
|
ret = nouveau_bo_move_prep(drm, bo, new_reg);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
if (drm_drv_uses_atomic_modeset(drm->dev))
|
|
mutex_lock(&cli->mutex);
|
|
else
|
|
mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
|
|
ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, ctx->interruptible);
|
|
if (ret == 0) {
|
|
ret = drm->ttm.move(chan, bo, &bo->mem, new_reg);
|
|
if (ret == 0) {
|
|
ret = nouveau_fence_new(chan, false, &fence);
|
|
if (ret == 0) {
|
|
ret = ttm_bo_move_accel_cleanup(bo,
|
|
&fence->base,
|
|
evict, false,
|
|
new_reg);
|
|
nouveau_fence_unref(&fence);
|
|
}
|
|
}
|
|
}
|
|
mutex_unlock(&cli->mutex);
|
|
return ret;
|
|
}
|
|
|
|
void
|
|
nouveau_bo_move_init(struct nouveau_drm *drm)
|
|
{
|
|
static const struct _method_table {
|
|
const char *name;
|
|
int engine;
|
|
s32 oclass;
|
|
int (*exec)(struct nouveau_channel *,
|
|
struct ttm_buffer_object *,
|
|
struct ttm_resource *, struct ttm_resource *);
|
|
int (*init)(struct nouveau_channel *, u32 handle);
|
|
} _methods[] = {
|
|
{ "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init },
|
|
{ "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init },
|
|
{ "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init },
|
|
{ "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init },
|
|
{ "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
|
|
{ "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
|
|
{ "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
|
|
{ "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
|
|
{ "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
|
|
{ "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
|
|
{ "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
|
|
{ "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
|
|
{ "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
|
|
{ "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
|
|
{ "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
|
|
{ "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
|
|
{ "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
|
|
{ "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
|
|
{ "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
|
|
{},
|
|
};
|
|
const struct _method_table *mthd = _methods;
|
|
const char *name = "CPU";
|
|
int ret;
|
|
|
|
do {
|
|
struct nouveau_channel *chan;
|
|
|
|
if (mthd->engine)
|
|
chan = drm->cechan;
|
|
else
|
|
chan = drm->channel;
|
|
if (chan == NULL)
|
|
continue;
|
|
|
|
ret = nvif_object_ctor(&chan->user, "ttmBoMove",
|
|
mthd->oclass | (mthd->engine << 16),
|
|
mthd->oclass, NULL, 0,
|
|
&drm->ttm.copy);
|
|
if (ret == 0) {
|
|
ret = mthd->init(chan, drm->ttm.copy.handle);
|
|
if (ret) {
|
|
nvif_object_dtor(&drm->ttm.copy);
|
|
continue;
|
|
}
|
|
|
|
drm->ttm.move = mthd->exec;
|
|
drm->ttm.chan = chan;
|
|
name = mthd->name;
|
|
break;
|
|
}
|
|
} while ((++mthd)->exec);
|
|
|
|
NV_INFO(drm, "MM: using %s for buffer copies\n", name);
|
|
}
|
|
|
|
static void
|
|
nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict,
|
|
struct ttm_resource *new_reg)
|
|
{
|
|
struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
|
|
struct nouveau_bo *nvbo = nouveau_bo(bo);
|
|
struct nouveau_vma *vma;
|
|
|
|
/* ttm can now (stupidly) pass the driver bos it didn't create... */
|
|
if (bo->destroy != nouveau_bo_del_ttm)
|
|
return;
|
|
|
|
nouveau_bo_del_io_reserve_lru(bo);
|
|
|
|
if (mem && new_reg->mem_type != TTM_PL_SYSTEM &&
|
|
mem->mem.page == nvbo->page) {
|
|
list_for_each_entry(vma, &nvbo->vma_list, head) {
|
|
nouveau_vma_map(vma, mem);
|
|
}
|
|
} else {
|
|
list_for_each_entry(vma, &nvbo->vma_list, head) {
|
|
WARN_ON(ttm_bo_wait(bo, false, false));
|
|
nouveau_vma_unmap(vma);
|
|
}
|
|
}
|
|
|
|
if (new_reg) {
|
|
if (new_reg->mm_node)
|
|
nvbo->offset = (new_reg->start << PAGE_SHIFT);
|
|
else
|
|
nvbo->offset = 0;
|
|
}
|
|
|
|
}
|
|
|
|
static int
|
|
nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg,
|
|
struct nouveau_drm_tile **new_tile)
|
|
{
|
|
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
|
|
struct drm_device *dev = drm->dev;
|
|
struct nouveau_bo *nvbo = nouveau_bo(bo);
|
|
u64 offset = new_reg->start << PAGE_SHIFT;
|
|
|
|
*new_tile = NULL;
|
|
if (new_reg->mem_type != TTM_PL_VRAM)
|
|
return 0;
|
|
|
|
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
|
|
*new_tile = nv10_bo_set_tiling(dev, offset, bo->base.size,
|
|
nvbo->mode, nvbo->zeta);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
|
|
struct nouveau_drm_tile *new_tile,
|
|
struct nouveau_drm_tile **old_tile)
|
|
{
|
|
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
|
|
struct drm_device *dev = drm->dev;
|
|
struct dma_fence *fence = dma_resv_get_excl(bo->base.resv);
|
|
|
|
nv10_bo_put_tile_region(dev, *old_tile, fence);
|
|
*old_tile = new_tile;
|
|
}
|
|
|
|
static int
|
|
nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
|
|
struct ttm_operation_ctx *ctx,
|
|
struct ttm_resource *new_reg,
|
|
struct ttm_place *hop)
|
|
{
|
|
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
|
|
struct nouveau_bo *nvbo = nouveau_bo(bo);
|
|
struct ttm_resource *old_reg = &bo->mem;
|
|
struct nouveau_drm_tile *new_tile = NULL;
|
|
int ret = 0;
|
|
|
|
|
|
if (new_reg->mem_type == TTM_PL_TT) {
|
|
ret = nouveau_ttm_tt_bind(bo->bdev, bo->ttm, new_reg);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
nouveau_bo_move_ntfy(bo, evict, new_reg);
|
|
ret = ttm_bo_wait_ctx(bo, ctx);
|
|
if (ret)
|
|
goto out_ntfy;
|
|
|
|
if (nvbo->bo.pin_count)
|
|
NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
|
|
|
|
if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
|
|
ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile);
|
|
if (ret)
|
|
goto out_ntfy;
|
|
}
|
|
|
|
/* Fake bo copy. */
|
|
if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
|
|
ttm_bo_move_null(bo, new_reg);
|
|
goto out;
|
|
}
|
|
|
|
if (old_reg->mem_type == TTM_PL_SYSTEM &&
|
|
new_reg->mem_type == TTM_PL_TT) {
|
|
ttm_bo_move_null(bo, new_reg);
|
|
goto out;
|
|
}
|
|
|
|
if (old_reg->mem_type == TTM_PL_TT &&
|
|
new_reg->mem_type == TTM_PL_SYSTEM) {
|
|
nouveau_ttm_tt_unbind(bo->bdev, bo->ttm);
|
|
ttm_resource_free(bo, &bo->mem);
|
|
ttm_bo_assign_mem(bo, new_reg);
|
|
goto out;
|
|
}
|
|
|
|
/* Hardware assisted copy. */
|
|
if (drm->ttm.move) {
|
|
if ((old_reg->mem_type == TTM_PL_SYSTEM &&
|
|
new_reg->mem_type == TTM_PL_VRAM) ||
|
|
(old_reg->mem_type == TTM_PL_VRAM &&
|
|
new_reg->mem_type == TTM_PL_SYSTEM)) {
|
|
hop->fpfn = 0;
|
|
hop->lpfn = 0;
|
|
hop->mem_type = TTM_PL_TT;
|
|
hop->flags = 0;
|
|
return -EMULTIHOP;
|
|
}
|
|
ret = nouveau_bo_move_m2mf(bo, evict, ctx,
|
|
new_reg);
|
|
} else
|
|
ret = -ENODEV;
|
|
|
|
if (ret) {
|
|
/* Fallback to software copy. */
|
|
ret = ttm_bo_move_memcpy(bo, ctx, new_reg);
|
|
}
|
|
|
|
out:
|
|
if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
|
|
if (ret)
|
|
nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
|
|
else
|
|
nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
|
|
}
|
|
out_ntfy:
|
|
if (ret) {
|
|
swap(*new_reg, bo->mem);
|
|
nouveau_bo_move_ntfy(bo, false, new_reg);
|
|
swap(*new_reg, bo->mem);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
|
|
{
|
|
struct nouveau_bo *nvbo = nouveau_bo(bo);
|
|
|
|
return drm_vma_node_verify_access(&nvbo->bo.base.vma_node,
|
|
filp->private_data);
|
|
}
|
|
|
|
static void
|
|
nouveau_ttm_io_mem_free_locked(struct nouveau_drm *drm,
|
|
struct ttm_resource *reg)
|
|
{
|
|
struct nouveau_mem *mem = nouveau_mem(reg);
|
|
|
|
if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
|
|
switch (reg->mem_type) {
|
|
case TTM_PL_TT:
|
|
if (mem->kind)
|
|
nvif_object_unmap_handle(&mem->mem.object);
|
|
break;
|
|
case TTM_PL_VRAM:
|
|
nvif_object_unmap_handle(&mem->mem.object);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
static int
|
|
nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *reg)
|
|
{
|
|
struct nouveau_drm *drm = nouveau_bdev(bdev);
|
|
struct nvkm_device *device = nvxx_device(&drm->client.device);
|
|
struct nouveau_mem *mem = nouveau_mem(reg);
|
|
struct nvif_mmu *mmu = &drm->client.mmu;
|
|
int ret;
|
|
|
|
mutex_lock(&drm->ttm.io_reserve_mutex);
|
|
retry:
|
|
switch (reg->mem_type) {
|
|
case TTM_PL_SYSTEM:
|
|
/* System memory */
|
|
ret = 0;
|
|
goto out;
|
|
case TTM_PL_TT:
|
|
#if IS_ENABLED(CONFIG_AGP)
|
|
if (drm->agp.bridge) {
|
|
reg->bus.offset = (reg->start << PAGE_SHIFT) +
|
|
drm->agp.base;
|
|
reg->bus.is_iomem = !drm->agp.cma;
|
|
reg->bus.caching = ttm_write_combined;
|
|
}
|
|
#endif
|
|
if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 ||
|
|
!mem->kind) {
|
|
/* untiled */
|
|
ret = 0;
|
|
break;
|
|
}
|
|
fallthrough; /* tiled memory */
|
|
case TTM_PL_VRAM:
|
|
reg->bus.offset = (reg->start << PAGE_SHIFT) +
|
|
device->func->resource_addr(device, 1);
|
|
reg->bus.is_iomem = true;
|
|
|
|
/* Some BARs do not support being ioremapped WC */
|
|
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
|
|
mmu->type[drm->ttm.type_vram].type & NVIF_MEM_UNCACHED)
|
|
reg->bus.caching = ttm_uncached;
|
|
else
|
|
reg->bus.caching = ttm_write_combined;
|
|
|
|
if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
|
|
union {
|
|
struct nv50_mem_map_v0 nv50;
|
|
struct gf100_mem_map_v0 gf100;
|
|
} args;
|
|
u64 handle, length;
|
|
u32 argc = 0;
|
|
|
|
switch (mem->mem.object.oclass) {
|
|
case NVIF_CLASS_MEM_NV50:
|
|
args.nv50.version = 0;
|
|
args.nv50.ro = 0;
|
|
args.nv50.kind = mem->kind;
|
|
args.nv50.comp = mem->comp;
|
|
argc = sizeof(args.nv50);
|
|
break;
|
|
case NVIF_CLASS_MEM_GF100:
|
|
args.gf100.version = 0;
|
|
args.gf100.ro = 0;
|
|
args.gf100.kind = mem->kind;
|
|
argc = sizeof(args.gf100);
|
|
break;
|
|
default:
|
|
WARN_ON(1);
|
|
break;
|
|
}
|
|
|
|
ret = nvif_object_map_handle(&mem->mem.object,
|
|
&args, argc,
|
|
&handle, &length);
|
|
if (ret != 1) {
|
|
if (WARN_ON(ret == 0))
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
reg->bus.offset = handle;
|
|
}
|
|
ret = 0;
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
}
|
|
|
|
out:
|
|
if (ret == -ENOSPC) {
|
|
struct nouveau_bo *nvbo;
|
|
|
|
nvbo = list_first_entry_or_null(&drm->ttm.io_reserve_lru,
|
|
typeof(*nvbo),
|
|
io_reserve_lru);
|
|
if (nvbo) {
|
|
list_del_init(&nvbo->io_reserve_lru);
|
|
drm_vma_node_unmap(&nvbo->bo.base.vma_node,
|
|
bdev->dev_mapping);
|
|
nouveau_ttm_io_mem_free_locked(drm, &nvbo->bo.mem);
|
|
goto retry;
|
|
}
|
|
|
|
}
|
|
mutex_unlock(&drm->ttm.io_reserve_mutex);
|
|
return ret;
|
|
}
|
|
|
|
static void
|
|
nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_resource *reg)
|
|
{
|
|
struct nouveau_drm *drm = nouveau_bdev(bdev);
|
|
|
|
mutex_lock(&drm->ttm.io_reserve_mutex);
|
|
nouveau_ttm_io_mem_free_locked(drm, reg);
|
|
mutex_unlock(&drm->ttm.io_reserve_mutex);
|
|
}
|
|
|
|
vm_fault_t nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
|
|
{
|
|
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
|
|
struct nouveau_bo *nvbo = nouveau_bo(bo);
|
|
struct nvkm_device *device = nvxx_device(&drm->client.device);
|
|
u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
|
|
int i, ret;
|
|
|
|
/* as long as the bo isn't in vram, and isn't tiled, we've got
|
|
* nothing to do here.
|
|
*/
|
|
if (bo->mem.mem_type != TTM_PL_VRAM) {
|
|
if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA ||
|
|
!nvbo->kind)
|
|
return 0;
|
|
|
|
if (bo->mem.mem_type != TTM_PL_SYSTEM)
|
|
return 0;
|
|
|
|
nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
|
|
|
|
} else {
|
|
/* make sure bo is in mappable vram */
|
|
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
|
|
bo->mem.start + bo->mem.num_pages < mappable)
|
|
return 0;
|
|
|
|
for (i = 0; i < nvbo->placement.num_placement; ++i) {
|
|
nvbo->placements[i].fpfn = 0;
|
|
nvbo->placements[i].lpfn = mappable;
|
|
}
|
|
|
|
for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
|
|
nvbo->busy_placements[i].fpfn = 0;
|
|
nvbo->busy_placements[i].lpfn = mappable;
|
|
}
|
|
|
|
nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0);
|
|
}
|
|
|
|
ret = nouveau_bo_validate(nvbo, false, false);
|
|
if (unlikely(ret == -EBUSY || ret == -ERESTARTSYS))
|
|
return VM_FAULT_NOPAGE;
|
|
else if (unlikely(ret))
|
|
return VM_FAULT_SIGBUS;
|
|
|
|
ttm_bo_move_to_lru_tail_unlocked(bo);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nouveau_ttm_tt_populate(struct ttm_bo_device *bdev,
|
|
struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
|
|
{
|
|
struct ttm_tt *ttm_dma = (void *)ttm;
|
|
struct nouveau_drm *drm;
|
|
struct device *dev;
|
|
bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
|
|
|
|
if (ttm_tt_is_populated(ttm))
|
|
return 0;
|
|
|
|
if (slave && ttm->sg) {
|
|
drm_prime_sg_to_dma_addr_array(ttm->sg, ttm_dma->dma_address,
|
|
ttm->num_pages);
|
|
return 0;
|
|
}
|
|
|
|
drm = nouveau_bdev(bdev);
|
|
dev = drm->dev->dev;
|
|
|
|
return ttm_pool_alloc(&drm->ttm.bdev.pool, ttm, ctx);
|
|
}
|
|
|
|
static void
|
|
nouveau_ttm_tt_unpopulate(struct ttm_bo_device *bdev,
|
|
struct ttm_tt *ttm)
|
|
{
|
|
struct nouveau_drm *drm;
|
|
struct device *dev;
|
|
bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
|
|
|
|
if (slave)
|
|
return;
|
|
|
|
drm = nouveau_bdev(bdev);
|
|
dev = drm->dev->dev;
|
|
|
|
return ttm_pool_free(&drm->ttm.bdev.pool, ttm);
|
|
}
|
|
|
|
static void
|
|
nouveau_ttm_tt_destroy(struct ttm_bo_device *bdev,
|
|
struct ttm_tt *ttm)
|
|
{
|
|
#if IS_ENABLED(CONFIG_AGP)
|
|
struct nouveau_drm *drm = nouveau_bdev(bdev);
|
|
if (drm->agp.bridge) {
|
|
ttm_agp_unbind(ttm);
|
|
ttm_tt_destroy_common(bdev, ttm);
|
|
ttm_agp_destroy(ttm);
|
|
return;
|
|
}
|
|
#endif
|
|
nouveau_sgdma_destroy(bdev, ttm);
|
|
}
|
|
|
|
void
|
|
nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
|
|
{
|
|
struct dma_resv *resv = nvbo->bo.base.resv;
|
|
|
|
if (exclusive)
|
|
dma_resv_add_excl_fence(resv, &fence->base);
|
|
else if (fence)
|
|
dma_resv_add_shared_fence(resv, &fence->base);
|
|
}
|
|
|
|
static void
|
|
nouveau_bo_delete_mem_notify(struct ttm_buffer_object *bo)
|
|
{
|
|
nouveau_bo_move_ntfy(bo, false, NULL);
|
|
}
|
|
|
|
struct ttm_bo_driver nouveau_bo_driver = {
|
|
.ttm_tt_create = &nouveau_ttm_tt_create,
|
|
.ttm_tt_populate = &nouveau_ttm_tt_populate,
|
|
.ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
|
|
.ttm_tt_destroy = &nouveau_ttm_tt_destroy,
|
|
.eviction_valuable = ttm_bo_eviction_valuable,
|
|
.evict_flags = nouveau_bo_evict_flags,
|
|
.delete_mem_notify = nouveau_bo_delete_mem_notify,
|
|
.move = nouveau_bo_move,
|
|
.verify_access = nouveau_bo_verify_access,
|
|
.io_mem_reserve = &nouveau_ttm_io_mem_reserve,
|
|
.io_mem_free = &nouveau_ttm_io_mem_free,
|
|
};
|