Kefeng Wang dbb58d0f79 arm64: dts: hip05: Add L2 cache topology ... The Hip05 SoC has four L2 cache for all 16 CPUs, every four cpus share one L2 cache, add them to the dtsi file so that the cache hierarchy can be probed. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>		2016-02-25 21:15:58 +08:00
..
boot	arm64: dts: hip05: Add L2 cache topology	2016-02-25 21:15:58 +08:00
configs	Third Round of Renesas ARM64 Based SoC Defconfig Updates for v4.5	2015-12-22 12:50:29 -08:00
crypto	arm64: crypto: reduce priority of core AES cipher	2015-11-18 12:09:08 +00:00
include	dma-mapping: always provide the dma_map_ops based implementation	2016-01-20 17:09:18 -08:00
kernel	arm64: insn: remove BUG_ON from codegen	2016-01-17 19:15:26 -05:00
kvm	arm64: KVM: Add support for 16-bit VMID	2015-12-18 10:15:12 +00:00
lib	arm64: add KASAN support	2015-10-12 17:46:36 +01:00
mm	arm64, thp: remove infrastructure for handling splitting PMDs	2016-01-15 17:56:32 -08:00
net	arm64: bpf: add extra pass to handle faulty codegen	2016-01-17 19:15:26 -05:00
xen	xen/arm: introduce HYPERVISOR_platform_op on arm and arm64	2015-12-21 14:40:56 +00:00
Kconfig	dma-mapping: always provide the dma_map_ops based implementation	2016-01-20 17:09:18 -08:00
Kconfig.debug	arch: consolidate CONFIG_STRICT_DEVM in lib/Kconfig.debug	2016-01-09 06:30:49 -08:00
Kconfig.platforms	ARM: SoC support for Tegra platforms for v4.5	2016-01-22 17:30:52 -08:00
Makefile	arm64 updates for 4.4:	2015-11-04 14:47:13 -08:00