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db9635cc14
Using the cached values has less latency for bare metal and SR-IOV, and prevents reading back bogus values if the engine is powergated. v2: fix typo in tile idx calculation Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
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acp | ||
amdgpu | ||
amdkfd | ||
include | ||
powerplay | ||
scheduler |