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4d5709a7b7
* master.kernel.org:/pub/scm/linux/kernel/git/davej/cpufreq: [CPUFREQ] Don't take semaphore in cpufreq_quick_get() [CPUFREQ] Support different families in fid/did to frequency conversion [CPUFREQ] cpufreq_stats: misc cpuinit section annotations [CPUFREQ] implement !CONFIG_CPU_FREQ stub for cpufreq_unregister_notifier() [CPUFREQ] mark hotplug notifier callback as __cpuinit [CPUFREQ] Only check for transition latency on problematic governors (kconfig fix) [CPUFREQ] allow ondemand and conservative cpufreq governors to be used as default [CPUFREQ] move policy's governor initialisation out of low-level drivers into cpufreq core [CPUFREQ] Longhaul - Add support for PM133 northbridge [CPUFREQ] x86: use num_online_nodes to get physical cpus numbers for
191 lines
4.2 KiB
C
191 lines
4.2 KiB
C
/*
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* sc520_freq.c: cpufreq driver for the AMD Elan sc520
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*
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* Copyright (C) 2005 Sean Young <sean@mess.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* Based on elanfreq.c
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*
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* 2005-03-30: - initial revision
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/cpufreq.h>
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#include <asm/msr.h>
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#include <asm/timex.h>
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#include <asm/io.h>
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#define MMCR_BASE 0xfffef000 /* The default base address */
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#define OFFS_CPUCTL 0x2 /* CPU Control Register */
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static __u8 __iomem *cpuctl;
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#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "sc520_freq", msg)
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static struct cpufreq_frequency_table sc520_freq_table[] = {
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{0x01, 100000},
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{0x02, 133000},
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{0, CPUFREQ_TABLE_END},
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};
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static unsigned int sc520_freq_get_cpu_frequency(unsigned int cpu)
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{
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u8 clockspeed_reg = *cpuctl;
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switch (clockspeed_reg & 0x03) {
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default:
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printk(KERN_ERR "sc520_freq: error: cpuctl register has unexpected value %02x\n", clockspeed_reg);
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case 0x01:
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return 100000;
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case 0x02:
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return 133000;
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}
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}
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static void sc520_freq_set_cpu_state (unsigned int state)
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{
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struct cpufreq_freqs freqs;
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u8 clockspeed_reg;
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freqs.old = sc520_freq_get_cpu_frequency(0);
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freqs.new = sc520_freq_table[state].frequency;
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freqs.cpu = 0; /* AMD Elan is UP */
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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dprintk("attempting to set frequency to %i kHz\n",
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sc520_freq_table[state].frequency);
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local_irq_disable();
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clockspeed_reg = *cpuctl & ~0x03;
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*cpuctl = clockspeed_reg | sc520_freq_table[state].index;
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local_irq_enable();
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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};
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static int sc520_freq_verify (struct cpufreq_policy *policy)
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{
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return cpufreq_frequency_table_verify(policy, &sc520_freq_table[0]);
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}
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static int sc520_freq_target (struct cpufreq_policy *policy,
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unsigned int target_freq,
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unsigned int relation)
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{
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unsigned int newstate = 0;
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if (cpufreq_frequency_table_target(policy, sc520_freq_table, target_freq, relation, &newstate))
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return -EINVAL;
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sc520_freq_set_cpu_state(newstate);
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return 0;
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}
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/*
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* Module init and exit code
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*/
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static int sc520_freq_cpu_init(struct cpufreq_policy *policy)
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{
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struct cpuinfo_x86 *c = cpu_data;
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int result;
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/* capability check */
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if (c->x86_vendor != X86_VENDOR_AMD ||
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c->x86 != 4 || c->x86_model != 9)
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return -ENODEV;
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/* cpuinfo and default policy values */
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policy->cpuinfo.transition_latency = 1000000; /* 1ms */
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policy->cur = sc520_freq_get_cpu_frequency(0);
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result = cpufreq_frequency_table_cpuinfo(policy, sc520_freq_table);
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if (result)
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return (result);
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cpufreq_frequency_table_get_attr(sc520_freq_table, policy->cpu);
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return 0;
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}
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static int sc520_freq_cpu_exit(struct cpufreq_policy *policy)
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{
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cpufreq_frequency_table_put_attr(policy->cpu);
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return 0;
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}
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static struct freq_attr* sc520_freq_attr[] = {
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&cpufreq_freq_attr_scaling_available_freqs,
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NULL,
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};
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static struct cpufreq_driver sc520_freq_driver = {
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.get = sc520_freq_get_cpu_frequency,
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.verify = sc520_freq_verify,
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.target = sc520_freq_target,
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.init = sc520_freq_cpu_init,
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.exit = sc520_freq_cpu_exit,
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.name = "sc520_freq",
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.owner = THIS_MODULE,
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.attr = sc520_freq_attr,
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};
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static int __init sc520_freq_init(void)
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{
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struct cpuinfo_x86 *c = cpu_data;
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int err;
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/* Test if we have the right hardware */
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if(c->x86_vendor != X86_VENDOR_AMD ||
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c->x86 != 4 || c->x86_model != 9) {
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dprintk("no Elan SC520 processor found!\n");
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return -ENODEV;
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}
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cpuctl = ioremap((unsigned long)(MMCR_BASE + OFFS_CPUCTL), 1);
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if(!cpuctl) {
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printk(KERN_ERR "sc520_freq: error: failed to remap memory\n");
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return -ENOMEM;
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}
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err = cpufreq_register_driver(&sc520_freq_driver);
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if (err)
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iounmap(cpuctl);
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return err;
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}
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static void __exit sc520_freq_exit(void)
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{
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cpufreq_unregister_driver(&sc520_freq_driver);
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iounmap(cpuctl);
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}
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Sean Young <sean@mess.org>");
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MODULE_DESCRIPTION("cpufreq driver for AMD's Elan sc520 CPU");
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module_init(sc520_freq_init);
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module_exit(sc520_freq_exit);
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