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12401fc28d
The command register of the PCI controller is not initialized correctly by the bootloader on some boards and this leads to non working PCI bus. Add code to initialize the command register from the Linux code to avoid this. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4916/ Signed-off-by: John Crispin <blogic@openwrt.org>
445 lines
9.8 KiB
C
445 lines
9.8 KiB
C
/*
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* Atheros AR724X PCI host controller driver
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*
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* Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
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* Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/spinlock.h>
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#include <linux/irq.h>
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#include <linux/pci.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#define AR724X_PCI_REG_RESET 0x18
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#define AR724X_PCI_REG_INT_STATUS 0x4c
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#define AR724X_PCI_REG_INT_MASK 0x50
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#define AR724X_PCI_RESET_LINK_UP BIT(0)
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#define AR724X_PCI_INT_DEV0 BIT(14)
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#define AR724X_PCI_IRQ_COUNT 1
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#define AR7240_BAR0_WAR_VALUE 0xffff
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#define AR724X_PCI_CMD_INIT (PCI_COMMAND_MEMORY | \
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PCI_COMMAND_MASTER | \
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PCI_COMMAND_INVALIDATE | \
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PCI_COMMAND_PARITY | \
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PCI_COMMAND_SERR | \
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PCI_COMMAND_FAST_BACK)
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struct ar724x_pci_controller {
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void __iomem *devcfg_base;
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void __iomem *ctrl_base;
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void __iomem *crp_base;
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int irq;
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int irq_base;
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bool link_up;
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bool bar0_is_cached;
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u32 bar0_value;
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spinlock_t lock;
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struct pci_controller pci_controller;
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struct resource io_res;
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struct resource mem_res;
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};
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static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
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{
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u32 reset;
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reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET);
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return reset & AR724X_PCI_RESET_LINK_UP;
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}
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static inline struct ar724x_pci_controller *
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pci_bus_to_ar724x_controller(struct pci_bus *bus)
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{
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struct pci_controller *hose;
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hose = (struct pci_controller *) bus->sysdata;
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return container_of(hose, struct ar724x_pci_controller, pci_controller);
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}
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static int ar724x_pci_local_write(struct ar724x_pci_controller *apc,
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int where, int size, u32 value)
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{
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unsigned long flags;
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void __iomem *base;
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u32 data;
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int s;
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WARN_ON(where & (size - 1));
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if (!apc->link_up)
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return PCIBIOS_DEVICE_NOT_FOUND;
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base = apc->crp_base;
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spin_lock_irqsave(&apc->lock, flags);
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data = __raw_readl(base + (where & ~3));
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switch (size) {
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case 1:
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s = ((where & 3) * 8);
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data &= ~(0xff << s);
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data |= ((value & 0xff) << s);
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break;
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case 2:
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s = ((where & 2) * 8);
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data &= ~(0xffff << s);
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data |= ((value & 0xffff) << s);
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break;
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case 4:
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data = value;
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break;
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default:
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spin_unlock_irqrestore(&apc->lock, flags);
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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__raw_writel(data, base + (where & ~3));
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/* flush write */
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__raw_readl(base + (where & ~3));
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spin_unlock_irqrestore(&apc->lock, flags);
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return PCIBIOS_SUCCESSFUL;
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}
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static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
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int size, uint32_t *value)
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{
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struct ar724x_pci_controller *apc;
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unsigned long flags;
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void __iomem *base;
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u32 data;
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apc = pci_bus_to_ar724x_controller(bus);
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if (!apc->link_up)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (devfn)
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return PCIBIOS_DEVICE_NOT_FOUND;
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base = apc->devcfg_base;
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spin_lock_irqsave(&apc->lock, flags);
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data = __raw_readl(base + (where & ~3));
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switch (size) {
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case 1:
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if (where & 1)
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data >>= 8;
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if (where & 2)
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data >>= 16;
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data &= 0xff;
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break;
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case 2:
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if (where & 2)
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data >>= 16;
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data &= 0xffff;
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break;
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case 4:
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break;
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default:
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spin_unlock_irqrestore(&apc->lock, flags);
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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spin_unlock_irqrestore(&apc->lock, flags);
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if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
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apc->bar0_is_cached) {
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/* use the cached value */
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*value = apc->bar0_value;
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} else {
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*value = data;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
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int size, uint32_t value)
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{
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struct ar724x_pci_controller *apc;
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unsigned long flags;
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void __iomem *base;
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u32 data;
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int s;
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apc = pci_bus_to_ar724x_controller(bus);
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if (!apc->link_up)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (devfn)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (soc_is_ar7240() && where == PCI_BASE_ADDRESS_0 && size == 4) {
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if (value != 0xffffffff) {
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/*
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* WAR for a hw issue. If the BAR0 register of the
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* device is set to the proper base address, the
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* memory space of the device is not accessible.
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*
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* Cache the intended value so it can be read back,
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* and write a SoC specific constant value to the
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* BAR0 register in order to make the device memory
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* accessible.
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*/
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apc->bar0_is_cached = true;
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apc->bar0_value = value;
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value = AR7240_BAR0_WAR_VALUE;
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} else {
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apc->bar0_is_cached = false;
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}
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}
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base = apc->devcfg_base;
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spin_lock_irqsave(&apc->lock, flags);
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data = __raw_readl(base + (where & ~3));
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switch (size) {
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case 1:
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s = ((where & 3) * 8);
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data &= ~(0xff << s);
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data |= ((value & 0xff) << s);
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break;
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case 2:
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s = ((where & 2) * 8);
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data &= ~(0xffff << s);
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data |= ((value & 0xffff) << s);
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break;
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case 4:
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data = value;
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break;
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default:
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spin_unlock_irqrestore(&apc->lock, flags);
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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__raw_writel(data, base + (where & ~3));
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/* flush write */
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__raw_readl(base + (where & ~3));
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spin_unlock_irqrestore(&apc->lock, flags);
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops ar724x_pci_ops = {
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.read = ar724x_pci_read,
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.write = ar724x_pci_write,
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};
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static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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struct ar724x_pci_controller *apc;
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void __iomem *base;
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u32 pending;
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apc = irq_get_handler_data(irq);
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base = apc->ctrl_base;
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pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
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__raw_readl(base + AR724X_PCI_REG_INT_MASK);
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if (pending & AR724X_PCI_INT_DEV0)
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generic_handle_irq(apc->irq_base + 0);
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else
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spurious_interrupt();
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}
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static void ar724x_pci_irq_unmask(struct irq_data *d)
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{
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struct ar724x_pci_controller *apc;
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void __iomem *base;
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int offset;
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u32 t;
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apc = irq_data_get_irq_chip_data(d);
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base = apc->ctrl_base;
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offset = apc->irq_base - d->irq;
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switch (offset) {
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case 0:
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t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
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__raw_writel(t | AR724X_PCI_INT_DEV0,
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base + AR724X_PCI_REG_INT_MASK);
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/* flush write */
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__raw_readl(base + AR724X_PCI_REG_INT_MASK);
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}
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}
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static void ar724x_pci_irq_mask(struct irq_data *d)
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{
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struct ar724x_pci_controller *apc;
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void __iomem *base;
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int offset;
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u32 t;
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apc = irq_data_get_irq_chip_data(d);
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base = apc->ctrl_base;
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offset = apc->irq_base - d->irq;
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switch (offset) {
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case 0:
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t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
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__raw_writel(t & ~AR724X_PCI_INT_DEV0,
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base + AR724X_PCI_REG_INT_MASK);
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/* flush write */
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__raw_readl(base + AR724X_PCI_REG_INT_MASK);
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t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
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__raw_writel(t | AR724X_PCI_INT_DEV0,
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base + AR724X_PCI_REG_INT_STATUS);
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/* flush write */
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__raw_readl(base + AR724X_PCI_REG_INT_STATUS);
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}
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}
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static struct irq_chip ar724x_pci_irq_chip = {
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.name = "AR724X PCI ",
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.irq_mask = ar724x_pci_irq_mask,
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.irq_unmask = ar724x_pci_irq_unmask,
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.irq_mask_ack = ar724x_pci_irq_mask,
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};
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static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,
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int id)
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{
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void __iomem *base;
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int i;
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base = apc->ctrl_base;
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__raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
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__raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
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apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);
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for (i = apc->irq_base;
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i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {
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irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
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handle_level_irq);
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irq_set_chip_data(i, apc);
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}
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irq_set_handler_data(apc->irq, apc);
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irq_set_chained_handler(apc->irq, ar724x_pci_irq_handler);
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}
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static int ar724x_pci_probe(struct platform_device *pdev)
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{
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struct ar724x_pci_controller *apc;
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struct resource *res;
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int id;
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id = pdev->id;
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if (id == -1)
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id = 0;
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apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller),
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GFP_KERNEL);
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if (!apc)
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return -ENOMEM;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base");
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if (!res)
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return -EINVAL;
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apc->ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
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if (apc->ctrl_base == NULL)
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return -EBUSY;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
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if (!res)
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return -EINVAL;
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apc->devcfg_base = devm_request_and_ioremap(&pdev->dev, res);
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if (!apc->devcfg_base)
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return -EBUSY;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crp_base");
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if (!res)
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return -EINVAL;
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apc->crp_base = devm_request_and_ioremap(&pdev->dev, res);
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if (apc->crp_base == NULL)
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return -EBUSY;
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apc->irq = platform_get_irq(pdev, 0);
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if (apc->irq < 0)
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return -EINVAL;
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spin_lock_init(&apc->lock);
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res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
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if (!res)
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return -EINVAL;
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apc->io_res.parent = res;
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apc->io_res.name = "PCI IO space";
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apc->io_res.start = res->start;
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apc->io_res.end = res->end;
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apc->io_res.flags = IORESOURCE_IO;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
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if (!res)
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return -EINVAL;
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apc->mem_res.parent = res;
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apc->mem_res.name = "PCI memory space";
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apc->mem_res.start = res->start;
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apc->mem_res.end = res->end;
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apc->mem_res.flags = IORESOURCE_MEM;
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apc->pci_controller.pci_ops = &ar724x_pci_ops;
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apc->pci_controller.io_resource = &apc->io_res;
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apc->pci_controller.mem_resource = &apc->mem_res;
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apc->link_up = ar724x_pci_check_link(apc);
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if (!apc->link_up)
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dev_warn(&pdev->dev, "PCIe link is down\n");
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ar724x_pci_irq_init(apc, id);
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ar724x_pci_local_write(apc, PCI_COMMAND, 4, AR724X_PCI_CMD_INIT);
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register_pci_controller(&apc->pci_controller);
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return 0;
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}
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static struct platform_driver ar724x_pci_driver = {
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.probe = ar724x_pci_probe,
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.driver = {
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.name = "ar724x-pci",
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.owner = THIS_MODULE,
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},
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};
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static int __init ar724x_pci_init(void)
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{
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return platform_driver_register(&ar724x_pci_driver);
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}
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postcore_initcall(ar724x_pci_init);
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