Samuel Holland daef19263f riscv: mm: Always use an ASID to flush mm contexts ... Even if multiple ASIDs are not supported, using the single-ASID variant of the sfence.vma instruction preserves TLB entries for global (kernel) pages. So it is always more efficient to use the single-ASID code path. Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20240327045035.368512-14-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2024-04-29 10:49:36 -07:00
..
cache-ops.c	riscv: split cache ops out of dma-noncoherent.c	2023-11-07 09:37:42 -08:00
cacheflush.c	riscv: Only send remote fences when some other CPU is online	2024-04-29 10:49:28 -07:00
context.c	riscv: mm: Preserve global TLB entries when switching contexts	2024-04-29 10:49:35 -07:00
dma-noncoherent.c	iommu: Remove struct iommu_ops *iommu from arch_setup_dma_ops()	2023-12-12 10:18:45 +01:00
extable.c	riscv: select DCACHE_WORD_ACCESS for efficient unaligned access HW	2024-01-09 20:18:20 -08:00
fault.c	RISC-V Patches for the 6.8 Merge Window, Part 1	2024-01-17 10:50:46 -08:00
hugetlbpage.c	riscv: Fix build error if !CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION	2024-02-22 12:28:25 -08:00
init.c	RISC-V Patches for the 6.9 Merge Window	2024-03-22 10:41:13 -07:00
kasan_init.c	percpu:	2024-01-18 15:01:28 -08:00
Makefile	riscv: mm: Combine the SMP and UP TLB flush code	2024-04-29 10:49:29 -07:00
pageattr.c	Merge remote-tracking branch 'palmer/fixes' into for-next	2024-01-09 20:10:32 -08:00
pgtable.c	riscv: Only flush the mm icache when setting an exec pte	2024-03-20 08:56:08 -07:00
physaddr.c	riscv: Use PUD/P4D/PGD pages for the linear mapping	2023-04-18 20:43:04 -07:00
pmem.c	RISC-V: capitalise CMO op macros	2023-11-05 09:11:23 -08:00
ptdump.c	mm: ptdump: have ptdump_check_wx() return bool	2024-02-22 10:24:47 -08:00
tlbflush.c	riscv: mm: Always use an ASID to flush mm contexts	2024-04-29 10:49:36 -07:00