Christophe Leroy da1adea075 powerpc/8xx: Allow STRICT_KERNEL_RwX with pinned TLB ... Pinned TLB are 8M. Now that there is no strict boundary anymore between text and RO data, it is possible to use 8M pinned executable TLB that covers both text and RO data. When PIN_TLB_DATA or PIN_TLB_TEXT is selected, enforce 8M RW data alignment and allow STRICT_KERNEL_RWX. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/c535fc97bf0dd8693192e25feeed8088701e00c6.1589866984.git.christophe.leroy@csgroup.eu		2020-05-26 22:22:23 +10:00
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8xx.c	powerpc/8xx: Allow STRICT_KERNEL_RwX with pinned TLB	2020-05-26 22:22:23 +10:00
40x.c	powerpc/32: refactor pmd_offset(pud_offset(pgd_offset...	2020-02-26 10:34:40 +11:00
44x.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152	2019-05-30 11:26:32 -07:00
book3e_hugetlbpage.c	powerpc/mm: move FSL_BOOK3 version of update_mmu_cache()	2019-08-20 21:22:14 +10:00
book3e_pgtable.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152	2019-05-30 11:26:32 -07:00
fsl_booke.c	powerpc/fsl_booke/kaslr: clear the original kernel if randomized	2019-11-13 19:27:44 +11:00
kaslr_booke.c	powerpc/fsl_booke/kaslr: support nokaslr cmdline parameter	2019-11-13 19:27:47 +11:00
Makefile	powerpc/fsl_booke/32: implement KASLR infrastructure	2019-11-13 19:27:40 +11:00
mmu_context.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152	2019-05-30 11:26:32 -07:00
tlb_low_64e.S	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152	2019-05-30 11:26:32 -07:00
tlb_low.S	powerpc/fsl_booke: Avoid creating duplicate tlb1 entry	2020-03-17 23:40:35 +11:00
tlb.c	powerpc/mm: make ioremap_bot common to all	2019-08-27 13:03:34 +10:00