linux/arch/x86/events
Janakarajan Natarajan ab027620e9 perf/x86/amd/uncore: Get correct number of cores sharing last level cache
In Family 17h, the number of cores sharing a cache level is obtained
from the Cache Properties CPUID leaf (0x8000001d) by passing in the
cache level in ECX. In prior families, a cache level of 2 was used to
determine this information.

To get the right information, irrespective of Family, iterate over
the cache levels using CPUID 0x8000001d. The last level cache is the
last value to return a non-zero value in EAX.

Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Borislav Petkov <bp@suse.de>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/5ab569025b39cdfaeca55b571d78c0fc800bdb69.1497452002.git.Janakarajan.Natarajan@amd.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-08-10 12:08:39 +02:00
..
amd perf/x86/amd/uncore: Get correct number of cores sharing last level cache 2017-08-10 12:08:39 +02:00
intel Merge branch 'perf/urgent' into perf/core, to pick up latest fixes and refresh the tree 2017-07-30 11:15:13 +02:00
core.c perf/x86: Fix RDPMC vs. mm_struct tracking 2017-08-10 12:01:08 +02:00
Kconfig perf/x86: Move Kconfig.perf and other perf configuration bits to events/Kconfig 2016-03-31 10:30:40 +02:00
Makefile perf/x86/events: Add an AMD-specific Makefile 2017-01-30 12:01:19 +01:00
msr.c Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 2016-07-30 12:56:26 -07:00
perf_event.h perf/x86/intel: Add Goldmont Plus CPU PMU support 2017-07-18 14:13:40 +02:00