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af9617b419
If we exit the for_each_of_cpu_node loop early, the reference on the
current node must be decremented, otherwise there is a leak.
Fixes: f756e362d9 ("clk: mvebu: add CPU clock driver for Armada 7K/8K")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/545df946044fc1fc05a4217cdf0054be7a79e49e.1619161112.git.christophe.jaillet@wanadoo.fr
Reviewed-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
365 lines
11 KiB
C
365 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Marvell Armada AP CPU Clock Controller
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*
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* Copyright (C) 2018 Marvell
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*
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* Omri Itach <omrii@marvell.com>
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* Gregory Clement <gregory.clement@bootlin.com>
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*/
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#define pr_fmt(fmt) "ap-cpu-clk: " fmt
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#include <linux/clk-provider.h>
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#include <linux/clk.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include "armada_ap_cp_helper.h"
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#define AP806_CPU_CLUSTER0 0
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#define AP806_CPU_CLUSTER1 1
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#define AP806_CPUS_PER_CLUSTER 2
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#define APN806_CPU1_MASK 0x1
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#define APN806_CLUSTER_NUM_OFFSET 8
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#define APN806_CLUSTER_NUM_MASK BIT(APN806_CLUSTER_NUM_OFFSET)
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#define APN806_MAX_DIVIDER 32
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/*
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* struct cpu_dfs_regs: CPU DFS register mapping
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* @divider_reg: full integer ratio from PLL frequency to CPU clock frequency
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* @force_reg: request to force new ratio regardless of relation to other clocks
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* @ratio_reg: central request to switch ratios
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*/
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struct cpu_dfs_regs {
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unsigned int divider_reg;
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unsigned int force_reg;
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unsigned int ratio_reg;
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unsigned int ratio_state_reg;
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unsigned int divider_mask;
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unsigned int cluster_offset;
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unsigned int force_mask;
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int divider_offset;
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int divider_ratio;
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int ratio_offset;
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int ratio_state_offset;
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int ratio_state_cluster_offset;
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};
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/* AP806 CPU DFS register mapping*/
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#define AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET 0x278
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#define AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET 0x280
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#define AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET 0x284
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#define AP806_CA72MP2_0_PLL_SR_REG_OFFSET 0xC94
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#define AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET 0x14
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#define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET 0
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#define AP806_PLL_CR_CPU_CLK_DIV_RATIO 0
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#define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK \
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(0x3f << AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET)
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#define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET 24
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#define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK \
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(0x1 << AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET)
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#define AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET 16
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#define AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET 0
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#define AP806_CA72MP2_0_PLL_RATIO_STATE 11
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#define STATUS_POLL_PERIOD_US 1
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#define STATUS_POLL_TIMEOUT_US 1000000
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#define to_ap_cpu_clk(_hw) container_of(_hw, struct ap_cpu_clk, hw)
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static const struct cpu_dfs_regs ap806_dfs_regs = {
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.divider_reg = AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET,
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.force_reg = AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET,
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.ratio_reg = AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET,
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.ratio_state_reg = AP806_CA72MP2_0_PLL_SR_REG_OFFSET,
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.divider_mask = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK,
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.cluster_offset = AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET,
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.force_mask = AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK,
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.divider_offset = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET,
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.divider_ratio = AP806_PLL_CR_CPU_CLK_DIV_RATIO,
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.ratio_offset = AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET,
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.ratio_state_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET,
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.ratio_state_cluster_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET,
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};
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/* AP807 CPU DFS register mapping */
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#define AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET 0x278
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#define AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET 0x27c
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#define AP807_DEVICE_GENERAL_STATUS_6_REG_OFFSET 0xc98
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#define AP807_CA72MP2_0_PLL_CR_CLUSTER_OFFSET 0x8
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#define AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET 18
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#define AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK \
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(0x3f << AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET)
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#define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET 12
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#define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK \
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(0x3f << AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET)
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#define AP807_PLL_CR_CPU_CLK_DIV_RATIO 3
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#define AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET 0
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#define AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK \
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(0x3 << AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET)
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#define AP807_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET 6
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#define AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_OFFSET 20
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#define AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_CLUSTER_OFFSET 3
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static const struct cpu_dfs_regs ap807_dfs_regs = {
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.divider_reg = AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET,
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.force_reg = AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET,
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.ratio_reg = AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET,
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.ratio_state_reg = AP807_DEVICE_GENERAL_STATUS_6_REG_OFFSET,
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.divider_mask = AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK,
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.cluster_offset = AP807_CA72MP2_0_PLL_CR_CLUSTER_OFFSET,
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.force_mask = AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK,
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.divider_offset = AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET,
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.divider_ratio = AP807_PLL_CR_CPU_CLK_DIV_RATIO,
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.ratio_offset = AP807_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET,
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.ratio_state_offset = AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_OFFSET,
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.ratio_state_cluster_offset =
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AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_CLUSTER_OFFSET
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};
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/*
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* struct ap806_clk: CPU cluster clock controller instance
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* @cluster: Cluster clock controller index
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* @clk_name: Cluster clock controller name
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* @dev : Cluster clock device
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* @hw: HW specific structure of Cluster clock controller
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* @pll_cr_base: CA72MP2 Register base (Device Sample at Reset register)
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*/
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struct ap_cpu_clk {
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unsigned int cluster;
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const char *clk_name;
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struct device *dev;
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struct clk_hw hw;
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struct regmap *pll_cr_base;
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const struct cpu_dfs_regs *pll_regs;
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};
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static unsigned long ap_cpu_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct ap_cpu_clk *clk = to_ap_cpu_clk(hw);
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unsigned int cpu_clkdiv_reg;
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int cpu_clkdiv_ratio;
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cpu_clkdiv_reg = clk->pll_regs->divider_reg +
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(clk->cluster * clk->pll_regs->cluster_offset);
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regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, &cpu_clkdiv_ratio);
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cpu_clkdiv_ratio &= clk->pll_regs->divider_mask;
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cpu_clkdiv_ratio >>= clk->pll_regs->divider_offset;
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return parent_rate / cpu_clkdiv_ratio;
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}
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static int ap_cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct ap_cpu_clk *clk = to_ap_cpu_clk(hw);
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int ret, reg, divider = parent_rate / rate;
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unsigned int cpu_clkdiv_reg, cpu_force_reg, cpu_ratio_reg, stable_bit;
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cpu_clkdiv_reg = clk->pll_regs->divider_reg +
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(clk->cluster * clk->pll_regs->cluster_offset);
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cpu_force_reg = clk->pll_regs->force_reg +
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(clk->cluster * clk->pll_regs->cluster_offset);
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cpu_ratio_reg = clk->pll_regs->ratio_reg +
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(clk->cluster * clk->pll_regs->cluster_offset);
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regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, ®);
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reg &= ~(clk->pll_regs->divider_mask);
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reg |= (divider << clk->pll_regs->divider_offset);
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/*
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* AP807 CPU divider has two channels with ratio 1:3 and divider_ratio
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* is 1. Otherwise, in the case of the AP806, divider_ratio is 0.
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*/
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if (clk->pll_regs->divider_ratio) {
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reg &= ~(AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK);
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reg |= ((divider * clk->pll_regs->divider_ratio) <<
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AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET);
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}
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regmap_write(clk->pll_cr_base, cpu_clkdiv_reg, reg);
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regmap_update_bits(clk->pll_cr_base, cpu_force_reg,
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clk->pll_regs->force_mask,
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clk->pll_regs->force_mask);
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regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg,
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BIT(clk->pll_regs->ratio_offset),
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BIT(clk->pll_regs->ratio_offset));
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stable_bit = BIT(clk->pll_regs->ratio_state_offset +
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clk->cluster *
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clk->pll_regs->ratio_state_cluster_offset);
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ret = regmap_read_poll_timeout(clk->pll_cr_base,
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clk->pll_regs->ratio_state_reg, reg,
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reg & stable_bit, STATUS_POLL_PERIOD_US,
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STATUS_POLL_TIMEOUT_US);
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if (ret)
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return ret;
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regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg,
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BIT(clk->pll_regs->ratio_offset), 0);
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return 0;
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}
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static long ap_cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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int divider = *parent_rate / rate;
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divider = min(divider, APN806_MAX_DIVIDER);
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return *parent_rate / divider;
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}
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static const struct clk_ops ap_cpu_clk_ops = {
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.recalc_rate = ap_cpu_clk_recalc_rate,
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.round_rate = ap_cpu_clk_round_rate,
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.set_rate = ap_cpu_clk_set_rate,
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};
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static int ap_cpu_clock_probe(struct platform_device *pdev)
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{
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int ret, nclusters = 0, cluster_index = 0;
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struct device *dev = &pdev->dev;
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struct device_node *dn, *np = dev->of_node;
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struct clk_hw_onecell_data *ap_cpu_data;
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struct ap_cpu_clk *ap_cpu_clk;
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struct regmap *regmap;
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regmap = syscon_node_to_regmap(np->parent);
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if (IS_ERR(regmap)) {
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pr_err("cannot get pll_cr_base regmap\n");
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return PTR_ERR(regmap);
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}
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/*
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* AP806 has 4 cpus and DFS for AP806 is controlled per
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* cluster (2 CPUs per cluster), cpu0 and cpu1 are fixed to
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* cluster0 while cpu2 and cpu3 are fixed to cluster1 whether
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* they are enabled or not. Since cpu0 is the boot cpu, then
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* cluster0 must exist. If cpu2 or cpu3 is enabled, cluster1
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* will exist and the cluster number is 2; otherwise the
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* cluster number is 1.
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*/
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nclusters = 1;
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for_each_of_cpu_node(dn) {
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int cpu, err;
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err = of_property_read_u32(dn, "reg", &cpu);
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if (WARN_ON(err)) {
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of_node_put(dn);
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return err;
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}
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/* If cpu2 or cpu3 is enabled */
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if (cpu & APN806_CLUSTER_NUM_MASK) {
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nclusters = 2;
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of_node_put(dn);
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break;
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}
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}
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/*
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* DFS for AP806 is controlled per cluster (2 CPUs per cluster),
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* so allocate structs per cluster
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*/
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ap_cpu_clk = devm_kcalloc(dev, nclusters, sizeof(*ap_cpu_clk),
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GFP_KERNEL);
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if (!ap_cpu_clk)
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return -ENOMEM;
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ap_cpu_data = devm_kzalloc(dev, struct_size(ap_cpu_data, hws,
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nclusters),
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GFP_KERNEL);
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if (!ap_cpu_data)
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return -ENOMEM;
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for_each_of_cpu_node(dn) {
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char *clk_name = "cpu-cluster-0";
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struct clk_init_data init;
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const char *parent_name;
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struct clk *parent;
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int cpu, err;
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err = of_property_read_u32(dn, "reg", &cpu);
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if (WARN_ON(err)) {
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of_node_put(dn);
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return err;
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}
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cluster_index = cpu & APN806_CLUSTER_NUM_MASK;
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cluster_index >>= APN806_CLUSTER_NUM_OFFSET;
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/* Initialize once for one cluster */
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if (ap_cpu_data->hws[cluster_index])
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continue;
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parent = of_clk_get(np, cluster_index);
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if (IS_ERR(parent)) {
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dev_err(dev, "Could not get the clock parent\n");
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of_node_put(dn);
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return -EINVAL;
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}
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parent_name = __clk_get_name(parent);
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clk_name[12] += cluster_index;
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ap_cpu_clk[cluster_index].clk_name =
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ap_cp_unique_name(dev, np->parent, clk_name);
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ap_cpu_clk[cluster_index].cluster = cluster_index;
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ap_cpu_clk[cluster_index].pll_cr_base = regmap;
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ap_cpu_clk[cluster_index].hw.init = &init;
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ap_cpu_clk[cluster_index].dev = dev;
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ap_cpu_clk[cluster_index].pll_regs = of_device_get_match_data(&pdev->dev);
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init.name = ap_cpu_clk[cluster_index].clk_name;
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init.ops = &ap_cpu_clk_ops;
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init.num_parents = 1;
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init.parent_names = &parent_name;
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ret = devm_clk_hw_register(dev, &ap_cpu_clk[cluster_index].hw);
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if (ret) {
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of_node_put(dn);
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return ret;
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}
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ap_cpu_data->hws[cluster_index] = &ap_cpu_clk[cluster_index].hw;
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}
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ap_cpu_data->num = cluster_index + 1;
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ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, ap_cpu_data);
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if (ret)
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dev_err(dev, "failed to register OF clock provider\n");
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return ret;
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}
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static const struct of_device_id ap_cpu_clock_of_match[] = {
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{
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.compatible = "marvell,ap806-cpu-clock",
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.data = &ap806_dfs_regs,
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},
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{
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.compatible = "marvell,ap807-cpu-clock",
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.data = &ap807_dfs_regs,
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},
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{ }
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};
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static struct platform_driver ap_cpu_clock_driver = {
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.probe = ap_cpu_clock_probe,
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.driver = {
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.name = "marvell-ap-cpu-clock",
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.of_match_table = ap_cpu_clock_of_match,
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.suppress_bind_attrs = true,
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},
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};
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builtin_platform_driver(ap_cpu_clock_driver);
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