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ccc9d4a6d6
Pull crypto update from Herbert Xu: "API: - Add support for cipher output IVs in testmgr - Add missing crypto_ahash_blocksize helper - Mark authenc and des ciphers as not allowed under FIPS. Algorithms: - Add CRC support to 842 compression - Add keywrap algorithm - A number of changes to the akcipher interface: + Separate functions for setting public/private keys. + Use SG lists. Drivers: - Add Intel SHA Extension optimised SHA1 and SHA256 - Use dma_map_sg instead of custom functions in crypto drivers - Add support for STM32 RNG - Add support for ST RNG - Add Device Tree support to exynos RNG driver - Add support for mxs-dcp crypto device on MX6SL - Add xts(aes) support to caam - Add ctr(aes) and xts(aes) support to qat - A large set of fixes from Russell King for the marvell/cesa driver" * 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (115 commits) crypto: asymmetric_keys - Fix unaligned access in x509_get_sig_params() crypto: akcipher - Don't #include crypto/public_key.h as the contents aren't used hwrng: exynos - Add Device Tree support hwrng: exynos - Fix missing configuration after suspend to RAM hwrng: exynos - Add timeout for waiting on init done dt-bindings: rng: Describe Exynos4 PRNG bindings crypto: marvell/cesa - use __le32 for hardware descriptors crypto: marvell/cesa - fix missing cpu_to_le32() in mv_cesa_dma_add_op() crypto: marvell/cesa - use memcpy_fromio()/memcpy_toio() crypto: marvell/cesa - use gfp_t for gfp flags crypto: marvell/cesa - use dma_addr_t for cur_dma crypto: marvell/cesa - use readl_relaxed()/writel_relaxed() crypto: caam - fix indentation of close braces crypto: caam - only export the state we really need to export crypto: caam - fix non-block aligned hash calculation crypto: caam - avoid needlessly saving and restoring caam_hash_ctx crypto: caam - print errno code when hash registration fails crypto: marvell/cesa - fix memory leak crypto: marvell/cesa - fix first-fragment handling in mv_cesa_ahash_dma_last_req() crypto: marvell/cesa - rearrange handling for sw padded hashes ...
377 lines
9.0 KiB
C
377 lines
9.0 KiB
C
/*
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* Cryptographic API.
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*
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* Glue code for the SHA1 Secure Hash Algorithm assembler implementation using
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* Supplemental SSE3 instructions.
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*
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* This file is based on sha1_generic.c
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*
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* Copyright (c) Alan Smithee.
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* Copyright (c) Andrew McDonald <andrew@mcdonald.org.uk>
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* Copyright (c) Jean-Francois Dive <jef@linuxbe.org>
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* Copyright (c) Mathias Krause <minipli@googlemail.com>
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* Copyright (c) Chandramouli Narayanan <mouli@linux.intel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <crypto/internal/hash.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/cryptohash.h>
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#include <linux/types.h>
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#include <crypto/sha.h>
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#include <crypto/sha1_base.h>
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#include <asm/fpu/api.h>
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typedef void (sha1_transform_fn)(u32 *digest, const char *data,
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unsigned int rounds);
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static int sha1_update(struct shash_desc *desc, const u8 *data,
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unsigned int len, sha1_transform_fn *sha1_xform)
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{
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struct sha1_state *sctx = shash_desc_ctx(desc);
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if (!irq_fpu_usable() ||
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(sctx->count % SHA1_BLOCK_SIZE) + len < SHA1_BLOCK_SIZE)
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return crypto_sha1_update(desc, data, len);
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/* make sure casting to sha1_block_fn() is safe */
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BUILD_BUG_ON(offsetof(struct sha1_state, state) != 0);
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kernel_fpu_begin();
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sha1_base_do_update(desc, data, len,
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(sha1_block_fn *)sha1_xform);
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kernel_fpu_end();
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return 0;
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}
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static int sha1_finup(struct shash_desc *desc, const u8 *data,
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unsigned int len, u8 *out, sha1_transform_fn *sha1_xform)
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{
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if (!irq_fpu_usable())
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return crypto_sha1_finup(desc, data, len, out);
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kernel_fpu_begin();
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if (len)
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sha1_base_do_update(desc, data, len,
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(sha1_block_fn *)sha1_xform);
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sha1_base_do_finalize(desc, (sha1_block_fn *)sha1_xform);
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kernel_fpu_end();
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return sha1_base_finish(desc, out);
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}
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asmlinkage void sha1_transform_ssse3(u32 *digest, const char *data,
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unsigned int rounds);
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static int sha1_ssse3_update(struct shash_desc *desc, const u8 *data,
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unsigned int len)
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{
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return sha1_update(desc, data, len,
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(sha1_transform_fn *) sha1_transform_ssse3);
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}
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static int sha1_ssse3_finup(struct shash_desc *desc, const u8 *data,
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unsigned int len, u8 *out)
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{
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return sha1_finup(desc, data, len, out,
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(sha1_transform_fn *) sha1_transform_ssse3);
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}
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/* Add padding and return the message digest. */
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static int sha1_ssse3_final(struct shash_desc *desc, u8 *out)
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{
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return sha1_ssse3_finup(desc, NULL, 0, out);
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}
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static struct shash_alg sha1_ssse3_alg = {
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.digestsize = SHA1_DIGEST_SIZE,
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.init = sha1_base_init,
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.update = sha1_ssse3_update,
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.final = sha1_ssse3_final,
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.finup = sha1_ssse3_finup,
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.descsize = sizeof(struct sha1_state),
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.base = {
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.cra_name = "sha1",
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.cra_driver_name = "sha1-ssse3",
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.cra_priority = 150,
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.cra_flags = CRYPTO_ALG_TYPE_SHASH,
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.cra_blocksize = SHA1_BLOCK_SIZE,
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.cra_module = THIS_MODULE,
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}
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};
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static int register_sha1_ssse3(void)
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{
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if (boot_cpu_has(X86_FEATURE_SSSE3))
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return crypto_register_shash(&sha1_ssse3_alg);
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return 0;
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}
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static void unregister_sha1_ssse3(void)
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{
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if (boot_cpu_has(X86_FEATURE_SSSE3))
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crypto_unregister_shash(&sha1_ssse3_alg);
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}
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#ifdef CONFIG_AS_AVX
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asmlinkage void sha1_transform_avx(u32 *digest, const char *data,
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unsigned int rounds);
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static int sha1_avx_update(struct shash_desc *desc, const u8 *data,
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unsigned int len)
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{
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return sha1_update(desc, data, len,
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(sha1_transform_fn *) sha1_transform_avx);
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}
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static int sha1_avx_finup(struct shash_desc *desc, const u8 *data,
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unsigned int len, u8 *out)
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{
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return sha1_finup(desc, data, len, out,
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(sha1_transform_fn *) sha1_transform_avx);
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}
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static int sha1_avx_final(struct shash_desc *desc, u8 *out)
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{
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return sha1_avx_finup(desc, NULL, 0, out);
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}
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static struct shash_alg sha1_avx_alg = {
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.digestsize = SHA1_DIGEST_SIZE,
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.init = sha1_base_init,
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.update = sha1_avx_update,
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.final = sha1_avx_final,
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.finup = sha1_avx_finup,
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.descsize = sizeof(struct sha1_state),
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.base = {
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.cra_name = "sha1",
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.cra_driver_name = "sha1-avx",
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.cra_priority = 160,
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.cra_flags = CRYPTO_ALG_TYPE_SHASH,
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.cra_blocksize = SHA1_BLOCK_SIZE,
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.cra_module = THIS_MODULE,
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}
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};
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static bool avx_usable(void)
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{
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if (!cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM, NULL)) {
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if (cpu_has_avx)
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pr_info("AVX detected but unusable.\n");
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return false;
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}
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return true;
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}
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static int register_sha1_avx(void)
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{
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if (avx_usable())
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return crypto_register_shash(&sha1_avx_alg);
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return 0;
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}
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static void unregister_sha1_avx(void)
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{
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if (avx_usable())
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crypto_unregister_shash(&sha1_avx_alg);
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}
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#else /* CONFIG_AS_AVX */
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static inline int register_sha1_avx(void) { return 0; }
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static inline void unregister_sha1_avx(void) { }
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#endif /* CONFIG_AS_AVX */
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#if defined(CONFIG_AS_AVX2) && (CONFIG_AS_AVX)
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#define SHA1_AVX2_BLOCK_OPTSIZE 4 /* optimal 4*64 bytes of SHA1 blocks */
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asmlinkage void sha1_transform_avx2(u32 *digest, const char *data,
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unsigned int rounds);
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static bool avx2_usable(void)
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{
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if (avx_usable() && boot_cpu_has(X86_FEATURE_AVX2)
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&& boot_cpu_has(X86_FEATURE_BMI1)
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&& boot_cpu_has(X86_FEATURE_BMI2))
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return true;
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return false;
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}
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static void sha1_apply_transform_avx2(u32 *digest, const char *data,
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unsigned int rounds)
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{
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/* Select the optimal transform based on data block size */
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if (rounds >= SHA1_AVX2_BLOCK_OPTSIZE)
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sha1_transform_avx2(digest, data, rounds);
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else
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sha1_transform_avx(digest, data, rounds);
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}
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static int sha1_avx2_update(struct shash_desc *desc, const u8 *data,
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unsigned int len)
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{
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return sha1_update(desc, data, len,
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(sha1_transform_fn *) sha1_apply_transform_avx2);
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}
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static int sha1_avx2_finup(struct shash_desc *desc, const u8 *data,
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unsigned int len, u8 *out)
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{
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return sha1_finup(desc, data, len, out,
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(sha1_transform_fn *) sha1_apply_transform_avx2);
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}
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static int sha1_avx2_final(struct shash_desc *desc, u8 *out)
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{
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return sha1_avx2_finup(desc, NULL, 0, out);
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}
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static struct shash_alg sha1_avx2_alg = {
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.digestsize = SHA1_DIGEST_SIZE,
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.init = sha1_base_init,
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.update = sha1_avx2_update,
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.final = sha1_avx2_final,
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.finup = sha1_avx2_finup,
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.descsize = sizeof(struct sha1_state),
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.base = {
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.cra_name = "sha1",
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.cra_driver_name = "sha1-avx2",
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.cra_priority = 170,
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.cra_flags = CRYPTO_ALG_TYPE_SHASH,
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.cra_blocksize = SHA1_BLOCK_SIZE,
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.cra_module = THIS_MODULE,
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}
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};
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static int register_sha1_avx2(void)
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{
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if (avx2_usable())
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return crypto_register_shash(&sha1_avx2_alg);
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return 0;
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}
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static void unregister_sha1_avx2(void)
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{
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if (avx2_usable())
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crypto_unregister_shash(&sha1_avx2_alg);
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}
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#else
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static inline int register_sha1_avx2(void) { return 0; }
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static inline void unregister_sha1_avx2(void) { }
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#endif
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#ifdef CONFIG_AS_SHA1_NI
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asmlinkage void sha1_ni_transform(u32 *digest, const char *data,
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unsigned int rounds);
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static int sha1_ni_update(struct shash_desc *desc, const u8 *data,
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unsigned int len)
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{
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return sha1_update(desc, data, len,
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(sha1_transform_fn *) sha1_ni_transform);
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}
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static int sha1_ni_finup(struct shash_desc *desc, const u8 *data,
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unsigned int len, u8 *out)
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{
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return sha1_finup(desc, data, len, out,
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(sha1_transform_fn *) sha1_ni_transform);
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}
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static int sha1_ni_final(struct shash_desc *desc, u8 *out)
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{
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return sha1_ni_finup(desc, NULL, 0, out);
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}
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static struct shash_alg sha1_ni_alg = {
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.digestsize = SHA1_DIGEST_SIZE,
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.init = sha1_base_init,
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.update = sha1_ni_update,
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.final = sha1_ni_final,
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.finup = sha1_ni_finup,
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.descsize = sizeof(struct sha1_state),
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.base = {
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.cra_name = "sha1",
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.cra_driver_name = "sha1-ni",
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.cra_priority = 250,
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.cra_flags = CRYPTO_ALG_TYPE_SHASH,
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.cra_blocksize = SHA1_BLOCK_SIZE,
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.cra_module = THIS_MODULE,
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}
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};
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static int register_sha1_ni(void)
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{
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if (boot_cpu_has(X86_FEATURE_SHA_NI))
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return crypto_register_shash(&sha1_ni_alg);
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return 0;
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}
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static void unregister_sha1_ni(void)
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{
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if (boot_cpu_has(X86_FEATURE_SHA_NI))
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crypto_unregister_shash(&sha1_ni_alg);
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}
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#else
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static inline int register_sha1_ni(void) { return 0; }
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static inline void unregister_sha1_ni(void) { }
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#endif
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static int __init sha1_ssse3_mod_init(void)
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{
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if (register_sha1_ssse3())
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goto fail;
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if (register_sha1_avx()) {
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unregister_sha1_ssse3();
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goto fail;
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}
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if (register_sha1_avx2()) {
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unregister_sha1_avx();
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unregister_sha1_ssse3();
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goto fail;
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}
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if (register_sha1_ni()) {
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unregister_sha1_avx2();
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unregister_sha1_avx();
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unregister_sha1_ssse3();
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goto fail;
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}
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return 0;
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fail:
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return -ENODEV;
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}
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static void __exit sha1_ssse3_mod_fini(void)
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{
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unregister_sha1_ni();
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unregister_sha1_avx2();
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unregister_sha1_avx();
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unregister_sha1_ssse3();
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}
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module_init(sha1_ssse3_mod_init);
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module_exit(sha1_ssse3_mod_fini);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm, Supplemental SSE3 accelerated");
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MODULE_ALIAS_CRYPTO("sha1");
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