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4917394e0c
The warning that a clock operation failed is only printed once. However, the function is called for various different clocks. The limit hides the warnings if different clocks are affected by the failures. The clock ops might fail if the firmware that handles the clocks is misconfigured. Therefore, replace the pr_warn_once with pr_debug to allow the user to see all errors if necessary. By default, hide the error messages and let drivers handle the errors. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.kernel.org/r/20220119115434.2042017-1-m.tretter@pengutronix.de Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
375 lines
9.8 KiB
C
375 lines
9.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Zynq UltraScale+ MPSoC Divider support
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*
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* Copyright (C) 2016-2019 Xilinx
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*
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* Adjustable divider clock implementation
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include "clk-zynqmp.h"
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/*
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* DOC: basic adjustable divider clock that cannot gate
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*
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* Traits of this clock:
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* prepare - clk_prepare only ensures that parents are prepared
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* enable - clk_enable only ensures that parents are enabled
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* rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
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* parent - fixed parent. No clk_set_parent support
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*/
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#define to_zynqmp_clk_divider(_hw) \
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container_of(_hw, struct zynqmp_clk_divider, hw)
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#define CLK_FRAC BIT(13) /* has a fractional parent */
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#define CUSTOM_FLAG_CLK_FRAC BIT(0) /* has a fractional parent in custom type flag */
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/**
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* struct zynqmp_clk_divider - adjustable divider clock
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* @hw: handle between common and hardware-specific interfaces
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* @flags: Hardware specific flags
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* @is_frac: The divider is a fractional divider
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* @clk_id: Id of clock
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* @div_type: divisor type (TYPE_DIV1 or TYPE_DIV2)
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* @max_div: maximum supported divisor (fetched from firmware)
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*/
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struct zynqmp_clk_divider {
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struct clk_hw hw;
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u8 flags;
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bool is_frac;
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u32 clk_id;
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u32 div_type;
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u16 max_div;
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};
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static inline int zynqmp_divider_get_val(unsigned long parent_rate,
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unsigned long rate, u16 flags)
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{
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int up, down;
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unsigned long up_rate, down_rate;
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if (flags & CLK_DIVIDER_POWER_OF_TWO) {
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up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
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down = DIV_ROUND_DOWN_ULL((u64)parent_rate, rate);
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up = __roundup_pow_of_two(up);
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down = __rounddown_pow_of_two(down);
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up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up);
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down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down);
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return (rate - up_rate) <= (down_rate - rate) ? up : down;
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} else {
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return DIV_ROUND_CLOSEST(parent_rate, rate);
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}
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}
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/**
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* zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
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* @hw: handle between common and hardware-specific interfaces
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* @parent_rate: rate of parent clock
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*
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* Return: 0 on success else error+reason
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*/
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static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
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const char *clk_name = clk_hw_get_name(hw);
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u32 clk_id = divider->clk_id;
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u32 div_type = divider->div_type;
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u32 div, value;
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int ret;
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ret = zynqmp_pm_clock_getdivider(clk_id, &div);
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if (ret)
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pr_debug("%s() get divider failed for %s, ret = %d\n",
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__func__, clk_name, ret);
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if (div_type == TYPE_DIV1)
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value = div & 0xFFFF;
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else
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value = div >> 16;
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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value = 1 << value;
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if (!value) {
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WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
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"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
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clk_name);
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return parent_rate;
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}
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return DIV_ROUND_UP_ULL(parent_rate, value);
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}
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static void zynqmp_get_divider2_val(struct clk_hw *hw,
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unsigned long rate,
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struct zynqmp_clk_divider *divider,
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int *bestdiv)
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{
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int div1;
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int div2;
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long error = LONG_MAX;
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unsigned long div1_prate;
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struct clk_hw *div1_parent_hw;
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struct clk_hw *div2_parent_hw = clk_hw_get_parent(hw);
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struct zynqmp_clk_divider *pdivider =
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to_zynqmp_clk_divider(div2_parent_hw);
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if (!pdivider)
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return;
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div1_parent_hw = clk_hw_get_parent(div2_parent_hw);
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if (!div1_parent_hw)
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return;
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div1_prate = clk_hw_get_rate(div1_parent_hw);
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*bestdiv = 1;
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for (div1 = 1; div1 <= pdivider->max_div;) {
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for (div2 = 1; div2 <= divider->max_div;) {
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long new_error = ((div1_prate / div1) / div2) - rate;
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if (abs(new_error) < abs(error)) {
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*bestdiv = div2;
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error = new_error;
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}
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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div2 = div2 << 1;
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else
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div2++;
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}
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if (pdivider->flags & CLK_DIVIDER_POWER_OF_TWO)
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div1 = div1 << 1;
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else
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div1++;
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}
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}
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/**
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* zynqmp_clk_divider_round_rate() - Round rate of divider clock
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* @hw: handle between common and hardware-specific interfaces
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* @rate: rate of clock to be set
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* @prate: rate of parent clock
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*
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* Return: 0 on success else error+reason
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*/
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static long zynqmp_clk_divider_round_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long *prate)
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{
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struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
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const char *clk_name = clk_hw_get_name(hw);
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u32 clk_id = divider->clk_id;
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u32 div_type = divider->div_type;
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u32 bestdiv;
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int ret;
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/* if read only, just return current value */
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if (divider->flags & CLK_DIVIDER_READ_ONLY) {
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ret = zynqmp_pm_clock_getdivider(clk_id, &bestdiv);
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if (ret)
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pr_debug("%s() get divider failed for %s, ret = %d\n",
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__func__, clk_name, ret);
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if (div_type == TYPE_DIV1)
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bestdiv = bestdiv & 0xFFFF;
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else
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bestdiv = bestdiv >> 16;
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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bestdiv = 1 << bestdiv;
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return DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
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}
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bestdiv = zynqmp_divider_get_val(*prate, rate, divider->flags);
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/*
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* In case of two divisors, compute best divider values and return
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* divider2 value based on compute value. div1 will be automatically
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* set to optimum based on required total divider value.
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*/
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if (div_type == TYPE_DIV2 &&
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(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
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zynqmp_get_divider2_val(hw, rate, divider, &bestdiv);
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}
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if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac)
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bestdiv = rate % *prate ? 1 : bestdiv;
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bestdiv = min_t(u32, bestdiv, divider->max_div);
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*prate = rate * bestdiv;
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return rate;
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}
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/**
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* zynqmp_clk_divider_set_rate() - Set rate of divider clock
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* @hw: handle between common and hardware-specific interfaces
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* @rate: rate of clock to be set
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* @parent_rate: rate of parent clock
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*
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* Return: 0 on success else error+reason
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*/
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static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
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const char *clk_name = clk_hw_get_name(hw);
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u32 clk_id = divider->clk_id;
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u32 div_type = divider->div_type;
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u32 value, div;
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int ret;
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value = zynqmp_divider_get_val(parent_rate, rate, divider->flags);
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if (div_type == TYPE_DIV1) {
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div = value & 0xFFFF;
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div |= 0xffff << 16;
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} else {
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div = 0xffff;
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div |= value << 16;
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}
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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div = __ffs(div);
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ret = zynqmp_pm_clock_setdivider(clk_id, div);
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if (ret)
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pr_debug("%s() set divider failed for %s, ret = %d\n",
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__func__, clk_name, ret);
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return ret;
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}
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static const struct clk_ops zynqmp_clk_divider_ops = {
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.recalc_rate = zynqmp_clk_divider_recalc_rate,
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.round_rate = zynqmp_clk_divider_round_rate,
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.set_rate = zynqmp_clk_divider_set_rate,
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};
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static const struct clk_ops zynqmp_clk_divider_ro_ops = {
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.recalc_rate = zynqmp_clk_divider_recalc_rate,
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.round_rate = zynqmp_clk_divider_round_rate,
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};
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/**
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* zynqmp_clk_get_max_divisor() - Get maximum supported divisor from firmware.
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* @clk_id: Id of clock
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* @type: Divider type
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*
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* Return: Maximum divisor of a clock if query data is successful
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* U16_MAX in case of query data is not success
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*/
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static u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type)
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{
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struct zynqmp_pm_query_data qdata = {0};
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ret;
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qdata.qid = PM_QID_CLOCK_GET_MAX_DIVISOR;
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qdata.arg1 = clk_id;
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qdata.arg2 = type;
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ret = zynqmp_pm_query_data(qdata, ret_payload);
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/*
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* To maintain backward compatibility return maximum possible value
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* (0xFFFF) if query for max divisor is not successful.
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*/
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if (ret)
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return U16_MAX;
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return ret_payload[1];
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}
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static inline unsigned long zynqmp_clk_map_divider_ccf_flags(
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const u32 zynqmp_type_flag)
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{
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unsigned long ccf_flag = 0;
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if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ONE_BASED)
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ccf_flag |= CLK_DIVIDER_ONE_BASED;
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if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO)
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ccf_flag |= CLK_DIVIDER_POWER_OF_TWO;
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if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ALLOW_ZERO)
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ccf_flag |= CLK_DIVIDER_ALLOW_ZERO;
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if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO)
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ccf_flag |= CLK_DIVIDER_HIWORD_MASK;
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if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST)
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ccf_flag |= CLK_DIVIDER_ROUND_CLOSEST;
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if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_READ_ONLY)
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ccf_flag |= CLK_DIVIDER_READ_ONLY;
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if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO)
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ccf_flag |= CLK_DIVIDER_MAX_AT_ZERO;
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return ccf_flag;
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}
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/**
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* zynqmp_clk_register_divider() - Register a divider clock
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* @name: Name of this clock
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* @clk_id: Id of clock
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* @parents: Name of this clock's parents
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* @num_parents: Number of parents
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* @nodes: Clock topology node
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*
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* Return: clock hardware to registered clock divider
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*/
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struct clk_hw *zynqmp_clk_register_divider(const char *name,
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u32 clk_id,
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const char * const *parents,
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u8 num_parents,
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const struct clock_topology *nodes)
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{
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struct zynqmp_clk_divider *div;
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struct clk_hw *hw;
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struct clk_init_data init;
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int ret;
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/* allocate the divider */
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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if (nodes->type_flag & CLK_DIVIDER_READ_ONLY)
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init.ops = &zynqmp_clk_divider_ro_ops;
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else
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init.ops = &zynqmp_clk_divider_ops;
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init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);
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init.parent_names = parents;
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init.num_parents = 1;
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/* struct clk_divider assignments */
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div->is_frac = !!((nodes->flag & CLK_FRAC) |
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(nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC));
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div->flags = zynqmp_clk_map_divider_ccf_flags(nodes->type_flag);
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div->hw.init = &init;
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div->clk_id = clk_id;
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div->div_type = nodes->type;
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/*
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* To achieve best possible rate, maximum limit of divider is required
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* while computation.
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*/
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div->max_div = zynqmp_clk_get_max_divisor(clk_id, nodes->type);
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hw = &div->hw;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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kfree(div);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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