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On recent Qualcomm platforms the QMP PIPE clocks feed into a set of muxes which must be parked to the "safe" source (bi_tcxo) when corresponding GDSC is turned off and on again. Currently this is handcoded in the PCIe driver by reparenting the gcc_pipe_N_clk_src clock. However the same code sequence should be applied in the pcie-qcom endpoint, USB3 and UFS drivers. Rather than copying this sequence over and over again, follow the example of clk_rcg2_shared_ops and implement this parking in the enable() and disable() clock operations. Supplement the regmap-mux with the new clk_regmap_phy_mux type, which implements such multiplexers as a simple gate clocks. This is possible since each of these multiplexers has just two clock sources: one coming from the PHY and a reference (XO) one. If the clock is running off the from-PHY source, report it as enabled. Report it as disabled otherwise (if it uses reference source). This way the PHY will disable the pipe clock before turning off the GDSC, which in turn would lead to disabling corresponding pipe_clk_src (and thus it being parked to a safe, reference clock source). And vice versa, after enabling the GDSC the PHY will enable the pipe clock, which would cause pipe_clk_src to be switched from a safe source to the working one. Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Johan Hovold <johan+linaro@kernel.org> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220608105238.2973600-2-dmitry.baryshkov@linaro.org
34 lines
999 B
C
34 lines
999 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022, Linaro Ltd.
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*/
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#ifndef __QCOM_CLK_REGMAP_PHY_MUX_H__
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#define __QCOM_CLK_REGMAP_PHY_MUX_H__
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#include "clk-regmap.h"
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/*
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* A clock implementation for PHY pipe and symbols clock muxes.
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*
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* If the clock is running off the from-PHY source, report it as enabled.
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* Report it as disabled otherwise (if it uses reference source).
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*
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* This way the PHY will disable the pipe clock before turning off the GDSC,
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* which in turn would lead to disabling corresponding pipe_clk_src (and thus
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* it being parked to a safe, reference clock source). And vice versa, after
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* enabling the GDSC the PHY will enable the pipe clock, which would cause
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* pipe_clk_src to be switched from a safe source to the working one.
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*
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* For some platforms this should be used for the UFS symbol_clk_src clocks
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* too.
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*/
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struct clk_regmap_phy_mux {
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u32 reg;
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struct clk_regmap clkr;
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};
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extern const struct clk_ops clk_regmap_phy_mux_ops;
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#endif
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