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bfc7249cc2
much later than usual due to several last minute bugs that had to be addressed. As usual the majority of changes are new drivers and modifications to existing drivers. The core recieved many fixes along with the groundwork for several large changes coming in the future which will better parition clock providers from clock consumers. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJUlMRQAAoJEDqPOy9afJhJgdUQAK4myJT0q10LSqe9piwzGVXg uDcIN5CTtbdYkvdGIfCjeqz3t+DClnAMPx2ZPIjC0Z1mIvqq+ViqwP5U8kKd7z1a WCKV8e5Et3O1WNbslzsx5Z2JYJNgzqr1xxWAOLTLh5rYxVwE5b946Yv4Whxa694I ugm4wNlibeN3H8pnyH8YEiWEtahtu7B5v/9WELpyREwNxw7ZA18MttEvWaamAPHG rAxhQCB3A3HaIvyg8KFdVmwOBZQMc2EWT00kJfdRWL4/iGAipKCnbuh1c8Pr/RQE XRg5Y+MuMLotoUELYYeZHtEmIlW3A+9gR6tLivswPpOP8/5BVUyA5Hh0yCGUqUHD s5Iheq7s7xnKEgIu9cD4tf1nCY41gw+4/I4pm47WLkaRgehcEBcAibVC3CupZ5pI hJiFqEKWPKEk8vAJ/mM+wCGI4w01+eoICBm4EG06Nwj4xkQcAVqE67ZvgVs1LrmL efqSxkWpNoetf0Q12cfePHmWtesGNdvljLdXQ54T4qH9HxNaI9/9eM6tyFTfrDSe BG5h7gbPr6/aM/1FfcWn5jQIfjEjPhQtSpCehs8pMf/pG5QZgftBtwe3p+yz7zXJ Q/v8xNEcZ7Ze6/9rJsAcbLzyzcdk9NzTlEMplzGBoUQFNiEXKoIjCDKAx39UFtMz EccWXvt9iNZZhmDcu0pU =jD84 -----END PGP SIGNATURE----- Merge tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux Pull clk framework updates from Mike Turquette: "This is much later than usual due to several last minute bugs that had to be addressed. As usual the majority of changes are new drivers and modifications to existing drivers. The core recieved many fixes along with the groundwork for several large changes coming in the future which will better parition clock providers from clock consumers" * tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux: (86 commits) clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated ARM: OMAP3: clock: fix boot breakage in legacy mode ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIs clk: Really fix deadlock with mmap_sem clk: mmp: fix sparse non static symbol warning clk: Change clk_ops->determine_rate to return a clk_hw as the best parent clk: change clk_debugfs_add_file to take a struct clk_hw clk: Don't expose __clk_get_accuracy clk: Don't try to use a struct clk* after it could have been freed clk: Remove unused function __clk_get_prepare_count clk: samsung: Fix double add of syscore ops after driver rebind clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi clk: samsung: exynos4415: Fix build with PM_SLEEP disabled clk: samsung: remove unnecessary inclusion of header files from clk.h clk: samsung: remove unnecessary CONFIG_OF from clk.c clk: samsung: Spelling s/bwtween/between/ clk: rockchip: Add support for the mmc clock phases using the framework clk: rockchip: add bindings for the mmc clocks clk: rockchip: rk3288 export i2s0_clkout for use in DT clk: rockchip: use clock ID for DMC (memory controller) on rk3288 ...
563 lines
14 KiB
Plaintext
563 lines
14 KiB
Plaintext
/*
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* Copyright 2014 Chen-Yu Tsai
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*
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* Chen-Yu Tsai <wens@csie.org>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public
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* License along with this file; if not, write to the Free
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* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/include/ "skeleton.dtsi"
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/ {
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interrupt-parent = <&gic>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &r_uart;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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};
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cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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};
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};
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memory {
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reg = <0x40000000 0x40000000>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc24M: osc24M_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: osc32k_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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pll1: clk@01c20000 {
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#clock-cells = <0>;
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compatible = "allwinner,sun8i-a23-pll1-clk";
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll1";
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};
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/* dummy clock until actually implemented */
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pll6: pll6_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <600000000>;
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clock-output-names = "pll6";
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};
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cpu: cpu_clk@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-cpu-clk";
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reg = <0x01c20050 0x4>;
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/*
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* PLL1 is listed twice here.
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* While it looks suspicious, it's actually documented
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* that way both in the datasheet and in the code from
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* Allwinner.
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*/
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clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
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clock-output-names = "cpu";
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};
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axi: axi_clk@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun8i-a23-axi-clk";
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reg = <0x01c20050 0x4>;
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clocks = <&cpu>;
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clock-output-names = "axi";
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};
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ahb1_mux: ahb1_mux_clk@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
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clock-output-names = "ahb1_mux";
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};
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ahb1: ahb1_clk@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-ahb-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&ahb1_mux>;
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clock-output-names = "ahb1";
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};
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apb1: apb1_clk@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-apb0-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&ahb1>;
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clock-output-names = "apb1";
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};
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ahb1_gates: clk@01c20060 {
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#clock-cells = <1>;
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compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
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reg = <0x01c20060 0x8>;
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clocks = <&ahb1>;
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clock-output-names = "ahb1_mipidsi", "ahb1_dma",
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"ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
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"ahb1_nand", "ahb1_sdram",
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"ahb1_hstimer", "ahb1_spi0",
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"ahb1_spi1", "ahb1_otg", "ahb1_ehci",
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"ahb1_ohci", "ahb1_ve", "ahb1_lcd",
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"ahb1_csi", "ahb1_be", "ahb1_fe",
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"ahb1_gpu", "ahb1_spinlock",
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"ahb1_drc";
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};
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apb1_gates: clk@01c20068 {
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#clock-cells = <1>;
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compatible = "allwinner,sun8i-a23-apb1-gates-clk";
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reg = <0x01c20068 0x4>;
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clocks = <&apb1>;
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clock-output-names = "apb1_codec", "apb1_pio",
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"apb1_daudio0", "apb1_daudio1";
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};
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apb2: clk@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-apb1-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
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clock-output-names = "apb2";
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};
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apb2_gates: clk@01c2006c {
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#clock-cells = <1>;
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compatible = "allwinner,sun8i-a23-apb2-gates-clk";
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reg = <0x01c2006c 0x4>;
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clocks = <&apb2>;
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clock-output-names = "apb2_i2c0", "apb2_i2c1",
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"apb2_i2c2", "apb2_uart0",
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"apb2_uart1", "apb2_uart2",
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"apb2_uart3", "apb2_uart4";
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};
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mmc0_clk: clk@01c20088 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6>;
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clock-output-names = "mmc0";
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};
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mmc1_clk: clk@01c2008c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c2008c 0x4>;
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clocks = <&osc24M>, <&pll6>;
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clock-output-names = "mmc1";
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};
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mmc2_clk: clk@01c20090 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c20090 0x4>;
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clocks = <&osc24M>, <&pll6>;
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clock-output-names = "mmc2";
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};
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};
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soc@01c00000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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dma: dma-controller@01c02000 {
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compatible = "allwinner,sun8i-a23-dma";
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reg = <0x01c02000 0x1000>;
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interrupts = <0 50 4>;
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clocks = <&ahb1_gates 6>;
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resets = <&ahb1_rst 6>;
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#dma-cells = <1>;
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};
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mmc0: mmc@01c0f000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&ahb1_gates 8>, <&mmc0_clk>;
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clock-names = "ahb", "mmc";
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resets = <&ahb1_rst 8>;
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reset-names = "ahb";
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interrupts = <0 60 4>;
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status = "disabled";
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};
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mmc1: mmc@01c10000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&ahb1_gates 9>, <&mmc1_clk>;
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clock-names = "ahb", "mmc";
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resets = <&ahb1_rst 9>;
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reset-names = "ahb";
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interrupts = <0 61 4>;
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status = "disabled";
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};
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mmc2: mmc@01c11000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c11000 0x1000>;
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clocks = <&ahb1_gates 10>, <&mmc2_clk>;
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clock-names = "ahb", "mmc";
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resets = <&ahb1_rst 10>;
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reset-names = "ahb";
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interrupts = <0 62 4>;
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status = "disabled";
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};
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pio: pinctrl@01c20800 {
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compatible = "allwinner,sun8i-a23-pinctrl";
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reg = <0x01c20800 0x400>;
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interrupts = <0 11 4>,
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<0 15 4>,
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<0 17 4>;
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clocks = <&apb1_gates 5>;
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gpio-controller;
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interrupt-controller;
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#address-cells = <1>;
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#size-cells = <0>;
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#gpio-cells = <3>;
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uart0_pins_a: uart0@0 {
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allwinner,pins = "PF2", "PF4";
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allwinner,function = "uart0";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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mmc0_pins_a: mmc0@0 {
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allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
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allwinner,function = "mmc0";
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allwinner,drive = <2>;
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allwinner,pull = <0>;
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};
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mmc1_pins_a: mmc1@0 {
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allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
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allwinner,function = "mmc1";
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allwinner,drive = <2>;
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allwinner,pull = <0>;
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};
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i2c0_pins_a: i2c0@0 {
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allwinner,pins = "PH2", "PH3";
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allwinner,function = "i2c0";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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i2c1_pins_a: i2c1@0 {
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allwinner,pins = "PH4", "PH5";
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allwinner,function = "i2c1";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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i2c2_pins_a: i2c2@0 {
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allwinner,pins = "PE12", "PE13";
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allwinner,function = "i2c2";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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};
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ahb1_rst: reset@01c202c0 {
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#reset-cells = <1>;
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compatible = "allwinner,sun6i-a31-clock-reset";
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reg = <0x01c202c0 0xc>;
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};
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apb1_rst: reset@01c202d0 {
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#reset-cells = <1>;
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compatible = "allwinner,sun6i-a31-clock-reset";
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reg = <0x01c202d0 0x4>;
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};
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apb2_rst: reset@01c202d8 {
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#reset-cells = <1>;
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compatible = "allwinner,sun6i-a31-clock-reset";
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reg = <0x01c202d8 0x4>;
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};
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timer@01c20c00 {
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compatible = "allwinner,sun4i-a10-timer";
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reg = <0x01c20c00 0xa0>;
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interrupts = <0 18 4>,
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<0 19 4>;
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clocks = <&osc24M>;
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};
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wdt0: watchdog@01c20ca0 {
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compatible = "allwinner,sun6i-a31-wdt";
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reg = <0x01c20ca0 0x20>;
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interrupts = <0 25 4>;
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};
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uart0: serial@01c28000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28000 0x400>;
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interrupts = <0 0 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb2_gates 16>;
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resets = <&apb2_rst 16>;
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dmas = <&dma 6>, <&dma 6>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uart1: serial@01c28400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28400 0x400>;
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interrupts = <0 1 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb2_gates 17>;
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resets = <&apb2_rst 17>;
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dmas = <&dma 7>, <&dma 7>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uart2: serial@01c28800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28800 0x400>;
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interrupts = <0 2 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb2_gates 18>;
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resets = <&apb2_rst 18>;
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dmas = <&dma 8>, <&dma 8>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uart3: serial@01c28c00 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28c00 0x400>;
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interrupts = <0 3 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb2_gates 19>;
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resets = <&apb2_rst 19>;
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|
dmas = <&dma 9>, <&dma 9>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@01c29000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29000 0x400>;
|
|
interrupts = <0 4 4>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb2_gates 20>;
|
|
resets = <&apb2_rst 20>;
|
|
dmas = <&dma 10>, <&dma 10>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@01c2ac00 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2ac00 0x400>;
|
|
interrupts = <0 6 4>;
|
|
clocks = <&apb2_gates 0>;
|
|
resets = <&apb2_rst 0>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c1: i2c@01c2b000 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2b000 0x400>;
|
|
interrupts = <0 7 4>;
|
|
clocks = <&apb2_gates 1>;
|
|
resets = <&apb2_rst 1>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c2: i2c@01c2b400 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2b400 0x400>;
|
|
interrupts = <0 8 4>;
|
|
clocks = <&apb2_gates 2>;
|
|
resets = <&apb2_rst 2>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
gic: interrupt-controller@01c81000 {
|
|
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
|
|
reg = <0x01c81000 0x1000>,
|
|
<0x01c82000 0x1000>,
|
|
<0x01c84000 0x2000>,
|
|
<0x01c86000 0x2000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <1 9 0xf04>;
|
|
};
|
|
|
|
rtc: rtc@01f00000 {
|
|
compatible = "allwinner,sun6i-a31-rtc";
|
|
reg = <0x01f00000 0x54>;
|
|
interrupts = <0 40 4>, <0 41 4>;
|
|
};
|
|
|
|
prcm@01f01400 {
|
|
compatible = "allwinner,sun8i-a23-prcm";
|
|
reg = <0x01f01400 0x200>;
|
|
|
|
ar100: ar100_clk {
|
|
compatible = "fixed-factor-clock";
|
|
#clock-cells = <0>;
|
|
clock-div = <1>;
|
|
clock-mult = <1>;
|
|
clocks = <&osc24M>;
|
|
clock-output-names = "ar100";
|
|
};
|
|
|
|
ahb0: ahb0_clk {
|
|
compatible = "fixed-factor-clock";
|
|
#clock-cells = <0>;
|
|
clock-div = <1>;
|
|
clock-mult = <1>;
|
|
clocks = <&ar100>;
|
|
clock-output-names = "ahb0";
|
|
};
|
|
|
|
apb0: apb0_clk {
|
|
compatible = "allwinner,sun8i-a23-apb0-clk";
|
|
#clock-cells = <0>;
|
|
clocks = <&ahb0>;
|
|
clock-output-names = "apb0";
|
|
};
|
|
|
|
apb0_gates: apb0_gates_clk {
|
|
compatible = "allwinner,sun8i-a23-apb0-gates-clk";
|
|
#clock-cells = <1>;
|
|
clocks = <&apb0>;
|
|
clock-output-names = "apb0_pio", "apb0_timer",
|
|
"apb0_rsb", "apb0_uart",
|
|
"apb0_i2c";
|
|
};
|
|
|
|
apb0_rst: apb0_rst {
|
|
compatible = "allwinner,sun6i-a31-clock-reset";
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|
|
|
|
r_uart: serial@01f02800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01f02800 0x400>;
|
|
interrupts = <0 38 4>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb0_gates 4>;
|
|
resets = <&apb0_rst 4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
r_pio: pinctrl@01f02c00 {
|
|
compatible = "allwinner,sun8i-a23-r-pinctrl";
|
|
reg = <0x01f02c00 0x400>;
|
|
interrupts = <0 45 4>;
|
|
clocks = <&apb0_gates 0>;
|
|
resets = <&apb0_rst 0>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#gpio-cells = <3>;
|
|
|
|
r_uart_pins_a: r_uart@0 {
|
|
allwinner,pins = "PL2", "PL3";
|
|
allwinner,function = "s_uart";
|
|
allwinner,drive = <0>;
|
|
allwinner,pull = <0>;
|
|
};
|
|
};
|
|
};
|
|
};
|