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The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which is muxed & gated then returned to the PHY as an input. Document the clock IDs to select the PIPE clock or the AUX clock, also enforce a second clock-output-names and a #clock-cells value of 1 for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-1-3ec0a966d52f@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> |
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| .. | ||
| phy-am654-serdes.h | ||
| phy-cadence.h | ||
| phy-imx8-pcie.h | ||
| phy-lan966x-serdes.h | ||
| phy-lantiq-vrx200-pcie.h | ||
| phy-ocelot-serdes.h | ||
| phy-pistachio-usb.h | ||
| phy-qcom-qmp.h | ||
| phy-qcom-qusb2.h | ||
| phy-ti.h | ||
| phy.h | ||