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2c86cd188f
files not using feature fixup don't need asm/feature-fixups.h files using feature fixup need asm/feature-fixups.h Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
157 lines
3.7 KiB
ArmAsm
157 lines
3.7 KiB
ArmAsm
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* Copyright SUSE Linux Products GmbH 2009
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*
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* Authors: Alexander Graf <agraf@suse.de>
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*/
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#include <asm/asm-compat.h>
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#include <asm/feature-fixups.h>
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#define SHADOW_SLB_ENTRY_LEN 0x10
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#define OFFSET_ESID(x) (SHADOW_SLB_ENTRY_LEN * x)
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#define OFFSET_VSID(x) ((SHADOW_SLB_ENTRY_LEN * x) + 8)
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/******************************************************************************
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* *
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* Entry code *
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* *
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*****************************************************************************/
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.macro LOAD_GUEST_SEGMENTS
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/* Required state:
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*
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* MSR = ~IR|DR
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* R13 = PACA
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* R1 = host R1
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* R2 = host R2
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* R3 = shadow vcpu
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* all other volatile GPRS = free except R4, R6
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* SVCPU[CR] = guest CR
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* SVCPU[XER] = guest XER
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* SVCPU[CTR] = guest CTR
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* SVCPU[LR] = guest LR
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*/
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BEGIN_FW_FTR_SECTION
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/* Declare SLB shadow as 0 entries big */
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ld r11, PACA_SLBSHADOWPTR(r13)
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li r8, 0
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stb r8, 3(r11)
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END_FW_FTR_SECTION_IFSET(FW_FEATURE_LPAR)
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/* Flush SLB */
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li r10, 0
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slbmte r10, r10
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slbia
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/* Fill SLB with our shadow */
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lbz r12, SVCPU_SLB_MAX(r3)
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mulli r12, r12, 16
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addi r12, r12, SVCPU_SLB
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add r12, r12, r3
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/* for (r11 = kvm_slb; r11 < kvm_slb + kvm_slb_size; r11+=slb_entry) */
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li r11, SVCPU_SLB
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add r11, r11, r3
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slb_loop_enter:
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ld r10, 0(r11)
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andis. r9, r10, SLB_ESID_V@h
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beq slb_loop_enter_skip
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ld r9, 8(r11)
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slbmte r9, r10
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slb_loop_enter_skip:
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addi r11, r11, 16
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cmpd cr0, r11, r12
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blt slb_loop_enter
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slb_do_enter:
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.endm
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/******************************************************************************
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* *
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* Exit code *
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* *
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*****************************************************************************/
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.macro LOAD_HOST_SEGMENTS
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/* Register usage at this point:
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*
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* R1 = host R1
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* R2 = host R2
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* R12 = exit handler id
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* R13 = shadow vcpu - SHADOW_VCPU_OFF [=PACA on PPC64]
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* SVCPU.* = guest *
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* SVCPU[CR] = guest CR
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* SVCPU[XER] = guest XER
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* SVCPU[CTR] = guest CTR
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* SVCPU[LR] = guest LR
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*
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*/
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/* Remove all SLB entries that are in use. */
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li r0, 0
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slbmte r0, r0
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slbia
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/* Restore bolted entries from the shadow */
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ld r11, PACA_SLBSHADOWPTR(r13)
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BEGIN_FW_FTR_SECTION
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/* Declare SLB shadow as SLB_NUM_BOLTED entries big */
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li r8, SLB_NUM_BOLTED
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stb r8, 3(r11)
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END_FW_FTR_SECTION_IFSET(FW_FEATURE_LPAR)
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/* Manually load all entries from shadow SLB */
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li r8, SLBSHADOW_SAVEAREA
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li r7, SLBSHADOW_SAVEAREA + 8
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.rept SLB_NUM_BOLTED
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LDX_BE r10, r11, r8
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cmpdi r10, 0
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beq 1f
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LDX_BE r9, r11, r7
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slbmte r9, r10
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1: addi r7, r7, SHADOW_SLB_ENTRY_LEN
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addi r8, r8, SHADOW_SLB_ENTRY_LEN
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.endr
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isync
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sync
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slb_do_exit:
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.endm
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