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f98a3dccfc
parisc, ia64 and powerpc32 are the only remaining architectures that
provide custom arch_{spin,read,write}_lock_flags() functions, which are
meant to re-enable interrupts while waiting for a spinlock.
However, none of these can actually run into this codepath, because
it is only called on architectures without CONFIG_GENERIC_LOCKBREAK,
or when CONFIG_DEBUG_LOCK_ALLOC is set without CONFIG_LOCKDEP, and none
of those combinations are possible on the three architectures.
Going back in the git history, it appears that arch/mn10300 may have
been able to run into this code path, but there is a good chance that
it never worked. On the architectures that still exist, it was
already impossible to hit back in 2008 after the introduction of
CONFIG_GENERIC_LOCKBREAK, and possibly earlier.
As this is all dead code, just remove it and the helper functions built
around it. For arch/ia64, the inline asm could be cleaned up, but
it seems safer to leave it untouched.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Helge Deller <deller@gmx.de> # parisc
Link: https://lore.kernel.org/r/20211022120058.1031690-1-arnd@kernel.org
135 lines
2.8 KiB
C
135 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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#include <asm/barrier.h>
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#include <asm/ldcw.h>
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#include <asm/processor.h>
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#include <asm/spinlock_types.h>
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static inline int arch_spin_is_locked(arch_spinlock_t *x)
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{
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volatile unsigned int *a = __ldcw_align(x);
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return READ_ONCE(*a) == 0;
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}
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static inline void arch_spin_lock(arch_spinlock_t *x)
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{
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volatile unsigned int *a;
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a = __ldcw_align(x);
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while (__ldcw(a) == 0)
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while (*a == 0)
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continue;
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}
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static inline void arch_spin_unlock(arch_spinlock_t *x)
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{
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volatile unsigned int *a;
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a = __ldcw_align(x);
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/* Release with ordered store. */
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__asm__ __volatile__("stw,ma %0,0(%1)" : : "r"(1), "r"(a) : "memory");
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}
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static inline int arch_spin_trylock(arch_spinlock_t *x)
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{
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volatile unsigned int *a;
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a = __ldcw_align(x);
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return __ldcw(a) != 0;
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}
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/*
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* Read-write spinlocks, allowing multiple readers but only one writer.
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* Unfair locking as Writers could be starved indefinitely by Reader(s)
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*
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* The spinlock itself is contained in @counter and access to it is
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* serialized with @lock_mutex.
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*/
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/* 1 - lock taken successfully */
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static inline int arch_read_trylock(arch_rwlock_t *rw)
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{
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int ret = 0;
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unsigned long flags;
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local_irq_save(flags);
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arch_spin_lock(&(rw->lock_mutex));
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/*
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* zero means writer holds the lock exclusively, deny Reader.
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* Otherwise grant lock to first/subseq reader
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*/
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if (rw->counter > 0) {
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rw->counter--;
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ret = 1;
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}
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arch_spin_unlock(&(rw->lock_mutex));
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local_irq_restore(flags);
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return ret;
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}
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/* 1 - lock taken successfully */
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static inline int arch_write_trylock(arch_rwlock_t *rw)
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{
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int ret = 0;
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unsigned long flags;
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local_irq_save(flags);
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arch_spin_lock(&(rw->lock_mutex));
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/*
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* If reader(s) hold lock (lock < __ARCH_RW_LOCK_UNLOCKED__),
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* deny writer. Otherwise if unlocked grant to writer
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* Hence the claim that Linux rwlocks are unfair to writers.
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* (can be starved for an indefinite time by readers).
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*/
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if (rw->counter == __ARCH_RW_LOCK_UNLOCKED__) {
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rw->counter = 0;
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ret = 1;
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}
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arch_spin_unlock(&(rw->lock_mutex));
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local_irq_restore(flags);
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return ret;
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}
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static inline void arch_read_lock(arch_rwlock_t *rw)
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{
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while (!arch_read_trylock(rw))
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cpu_relax();
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}
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static inline void arch_write_lock(arch_rwlock_t *rw)
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{
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while (!arch_write_trylock(rw))
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cpu_relax();
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}
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static inline void arch_read_unlock(arch_rwlock_t *rw)
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{
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unsigned long flags;
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local_irq_save(flags);
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arch_spin_lock(&(rw->lock_mutex));
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rw->counter++;
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arch_spin_unlock(&(rw->lock_mutex));
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local_irq_restore(flags);
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}
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static inline void arch_write_unlock(arch_rwlock_t *rw)
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{
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unsigned long flags;
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local_irq_save(flags);
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arch_spin_lock(&(rw->lock_mutex));
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rw->counter = __ARCH_RW_LOCK_UNLOCKED__;
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arch_spin_unlock(&(rw->lock_mutex));
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local_irq_restore(flags);
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}
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#endif /* __ASM_SPINLOCK_H */
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