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63f0733d07
Currently, if CONFIG_SCSI_HISI_SAS_DEBUGFS_DEFAULT_ENABLE is enabled, the
memory space used by DFX is allocated during device initialization, which
occupies a large number of memory resources. The memory usage before and
after the driver is loaded is as follows:
Memory usage before the driver is loaded:
$ free -m
total used free shared buff/cache available
Mem: 867352 2578 864037 11 735 861681
Swap: 4095 0 4095
Memory usage after the driver which include 4 HBAs is loaded:
$ insmod hisi_sas_v3_hw.ko
$ free -m
total used free shared buff/cache available
Mem: 867352 4760 861848 11 743 859495
Swap: 4095 0 4095
The driver with 4 HBAs connected will allocate about 110 MB of memory
without enabling debugfs.
Therefore, to avoid wasting memory resources, DFX memory is allocated
during dump triggering. The dump may fail due to memory allocation
failure. After this change, each dump costs about 10 MB of memory, and each
dump lasts about 100 ms.
Signed-off-by: Yihang Li <liyihang9@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Link: https://lore.kernel.org/r/1694571327-78697-4-git-send-email-chenxiang66@hisilicon.com
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
673 lines
18 KiB
C
673 lines
18 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2015 Linaro Ltd.
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* Copyright (c) 2015 Hisilicon Limited.
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*/
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#ifndef _HISI_SAS_H_
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#define _HISI_SAS_H_
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#include <linux/acpi.h>
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#include <linux/blk-mq.h>
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#include <linux/blk-mq-pci.h>
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#include <linux/clk.h>
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#include <linux/debugfs.h>
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#include <linux/dmapool.h>
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#include <linux/iopoll.h>
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#include <linux/irq.h>
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#include <linux/lcm.h>
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#include <linux/libata.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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#include <linux/timer.h>
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#include <scsi/sas_ata.h>
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#include <scsi/libsas.h>
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#define HISI_SAS_MAX_PHYS 9
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#define HISI_SAS_MAX_QUEUES 32
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#define HISI_SAS_QUEUE_SLOTS 4096
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#define HISI_SAS_MAX_ITCT_ENTRIES 1024
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#define HISI_SAS_MAX_DEVICES HISI_SAS_MAX_ITCT_ENTRIES
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#define HISI_SAS_RESETTING_BIT 0
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#define HISI_SAS_REJECT_CMD_BIT 1
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#define HISI_SAS_PM_BIT 2
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#define HISI_SAS_HW_FAULT_BIT 3
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#define HISI_SAS_MAX_COMMANDS (HISI_SAS_QUEUE_SLOTS)
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#define HISI_SAS_RESERVED_IPTT 96
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#define HISI_SAS_UNRESERVED_IPTT \
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(HISI_SAS_MAX_COMMANDS - HISI_SAS_RESERVED_IPTT)
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#define HISI_SAS_IOST_ITCT_CACHE_NUM 64
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#define HISI_SAS_IOST_ITCT_CACHE_DW_SZ 10
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#define HISI_SAS_FIFO_DATA_DW_SIZE 32
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#define HISI_SAS_STATUS_BUF_SZ (sizeof(struct hisi_sas_status_buffer))
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#define HISI_SAS_COMMAND_TABLE_SZ (sizeof(union hisi_sas_command_table))
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#define hisi_sas_status_buf_addr(buf) \
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((buf) + offsetof(struct hisi_sas_slot_buf_table, status_buffer))
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#define hisi_sas_status_buf_addr_mem(slot) hisi_sas_status_buf_addr((slot)->buf)
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#define hisi_sas_status_buf_addr_dma(slot) \
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hisi_sas_status_buf_addr((slot)->buf_dma)
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#define hisi_sas_cmd_hdr_addr(buf) \
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((buf) + offsetof(struct hisi_sas_slot_buf_table, command_header))
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#define hisi_sas_cmd_hdr_addr_mem(slot) hisi_sas_cmd_hdr_addr((slot)->buf)
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#define hisi_sas_cmd_hdr_addr_dma(slot) hisi_sas_cmd_hdr_addr((slot)->buf_dma)
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#define hisi_sas_sge_addr(buf) \
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((buf) + offsetof(struct hisi_sas_slot_buf_table, sge_page))
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#define hisi_sas_sge_addr_mem(slot) hisi_sas_sge_addr((slot)->buf)
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#define hisi_sas_sge_addr_dma(slot) hisi_sas_sge_addr((slot)->buf_dma)
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#define hisi_sas_sge_dif_addr(buf) \
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((buf) + offsetof(struct hisi_sas_slot_dif_buf_table, sge_dif_page))
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#define hisi_sas_sge_dif_addr_mem(slot) hisi_sas_sge_dif_addr((slot)->buf)
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#define hisi_sas_sge_dif_addr_dma(slot) hisi_sas_sge_dif_addr((slot)->buf_dma)
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#define HISI_SAS_MAX_SSP_RESP_SZ (sizeof(struct ssp_frame_hdr) + 1024)
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#define HISI_SAS_MAX_SMP_RESP_SZ 1028
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#define HISI_SAS_MAX_STP_RESP_SZ 28
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#define HISI_SAS_SATA_PROTOCOL_NONDATA 0x1
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#define HISI_SAS_SATA_PROTOCOL_PIO 0x2
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#define HISI_SAS_SATA_PROTOCOL_DMA 0x4
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#define HISI_SAS_SATA_PROTOCOL_FPDMA 0x8
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#define HISI_SAS_SATA_PROTOCOL_ATAPI 0x10
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#define HISI_SAS_DIF_PROT_MASK (SHOST_DIF_TYPE1_PROTECTION | \
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SHOST_DIF_TYPE2_PROTECTION | \
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SHOST_DIF_TYPE3_PROTECTION)
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#define HISI_SAS_DIX_PROT_MASK (SHOST_DIX_TYPE1_PROTECTION | \
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SHOST_DIX_TYPE2_PROTECTION | \
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SHOST_DIX_TYPE3_PROTECTION)
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#define HISI_SAS_PROT_MASK (HISI_SAS_DIF_PROT_MASK | HISI_SAS_DIX_PROT_MASK)
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#define HISI_SAS_WAIT_PHYUP_TIMEOUT (30 * HZ)
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#define HISI_SAS_CLEAR_ITCT_TIMEOUT (20 * HZ)
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struct hisi_hba;
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enum {
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PORT_TYPE_SAS = (1U << 1),
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PORT_TYPE_SATA = (1U << 0),
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};
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enum dev_status {
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HISI_SAS_DEV_INIT,
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HISI_SAS_DEV_NORMAL,
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HISI_SAS_DEV_NCQ_ERR,
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};
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enum {
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HISI_SAS_INT_ABT_CMD = 0,
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HISI_SAS_INT_ABT_DEV = 1,
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};
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enum hisi_sas_dev_type {
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HISI_SAS_DEV_TYPE_STP = 0,
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HISI_SAS_DEV_TYPE_SSP,
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HISI_SAS_DEV_TYPE_SATA,
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};
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struct hisi_sas_hw_error {
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u32 irq_msk;
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u32 msk;
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int shift;
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const char *msg;
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int reg;
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const struct hisi_sas_hw_error *sub;
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};
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struct hisi_sas_rst {
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struct hisi_hba *hisi_hba;
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struct completion *completion;
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struct work_struct work;
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bool done;
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};
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#define HISI_SAS_RST_WORK_INIT(r, c) \
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{ .hisi_hba = hisi_hba, \
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.completion = &c, \
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.work = __WORK_INITIALIZER(r.work, \
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hisi_sas_sync_rst_work_handler), \
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.done = false, \
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}
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#define HISI_SAS_DECLARE_RST_WORK_ON_STACK(r) \
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DECLARE_COMPLETION_ONSTACK(c); \
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struct hisi_sas_rst r = HISI_SAS_RST_WORK_INIT(r, c)
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enum hisi_sas_bit_err_type {
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HISI_SAS_ERR_SINGLE_BIT_ECC = 0x0,
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HISI_SAS_ERR_MULTI_BIT_ECC = 0x1,
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};
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enum hisi_sas_phy_event {
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HISI_PHYE_PHY_UP = 0U,
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HISI_PHYE_LINK_RESET,
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HISI_PHYE_PHY_UP_PM,
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HISI_PHYES_NUM,
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};
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struct hisi_sas_debugfs_fifo {
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u32 signal_sel;
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u32 dump_msk;
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u32 dump_mode;
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u32 trigger;
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u32 trigger_msk;
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u32 trigger_mode;
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u32 rd_data[HISI_SAS_FIFO_DATA_DW_SIZE];
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};
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struct hisi_sas_phy {
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struct work_struct works[HISI_PHYES_NUM];
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struct hisi_hba *hisi_hba;
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struct hisi_sas_port *port;
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struct asd_sas_phy sas_phy;
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struct sas_identify identify;
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struct completion *reset_completion;
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struct timer_list timer;
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spinlock_t lock;
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u64 port_id; /* from hw */
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u64 frame_rcvd_size;
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u8 frame_rcvd[32];
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u8 phy_attached;
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u8 in_reset;
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u8 reserved[2];
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u32 phy_type;
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u32 code_violation_err_count;
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enum sas_linkrate minimum_linkrate;
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enum sas_linkrate maximum_linkrate;
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int enable;
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int wait_phyup_cnt;
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atomic_t down_cnt;
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/* Trace FIFO */
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struct hisi_sas_debugfs_fifo fifo;
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};
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struct hisi_sas_port {
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struct asd_sas_port sas_port;
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u8 port_attached;
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u8 id; /* from hw */
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};
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struct hisi_sas_cq {
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struct hisi_hba *hisi_hba;
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const struct cpumask *irq_mask;
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int rd_point;
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int id;
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int irq_no;
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spinlock_t poll_lock;
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};
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struct hisi_sas_dq {
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struct hisi_hba *hisi_hba;
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struct list_head list;
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spinlock_t lock;
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int wr_point;
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int id;
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};
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struct hisi_sas_device {
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struct hisi_hba *hisi_hba;
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struct domain_device *sas_device;
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struct completion *completion;
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struct hisi_sas_dq *dq;
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struct list_head list;
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enum sas_device_type dev_type;
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enum dev_status dev_status;
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int device_id;
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int sata_idx;
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spinlock_t lock; /* For protecting slots */
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};
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struct hisi_sas_slot {
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struct list_head entry;
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struct list_head delivery;
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struct sas_task *task;
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struct hisi_sas_port *port;
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u64 n_elem;
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u64 n_elem_dif;
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int dlvry_queue;
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int dlvry_queue_slot;
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int cmplt_queue;
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int cmplt_queue_slot;
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int abort;
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int ready;
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int device_id;
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void *cmd_hdr;
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dma_addr_t cmd_hdr_dma;
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struct timer_list internal_abort_timer;
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bool is_internal;
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struct sas_tmf_task *tmf;
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/* Do not reorder/change members after here */
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void *buf;
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dma_addr_t buf_dma;
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u16 idx;
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};
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struct hisi_sas_iost_itct_cache {
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u32 data[HISI_SAS_IOST_ITCT_CACHE_DW_SZ];
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};
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enum hisi_sas_debugfs_reg_array_member {
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DEBUGFS_GLOBAL = 0,
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DEBUGFS_AXI,
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DEBUGFS_RAS,
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DEBUGFS_REGS_NUM
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};
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enum hisi_sas_debugfs_cache_type {
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HISI_SAS_ITCT_CACHE,
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HISI_SAS_IOST_CACHE,
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};
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enum hisi_sas_debugfs_bist_ffe_cfg {
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FFE_SAS_1_5_GBPS,
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FFE_SAS_3_0_GBPS,
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FFE_SAS_6_0_GBPS,
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FFE_SAS_12_0_GBPS,
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FFE_RESV,
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FFE_SATA_1_5_GBPS,
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FFE_SATA_3_0_GBPS,
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FFE_SATA_6_0_GBPS,
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FFE_CFG_MAX
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};
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enum hisi_sas_debugfs_bist_fixed_code {
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FIXED_CODE,
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FIXED_CODE_1,
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FIXED_CODE_MAX
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};
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enum {
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HISI_SAS_BIST_CODE_MODE_PRBS7,
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HISI_SAS_BIST_CODE_MODE_PRBS23,
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HISI_SAS_BIST_CODE_MODE_PRBS31,
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HISI_SAS_BIST_CODE_MODE_JTPAT,
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HISI_SAS_BIST_CODE_MODE_CJTPAT,
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HISI_SAS_BIST_CODE_MODE_SCRAMBED_0,
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HISI_SAS_BIST_CODE_MODE_TRAIN,
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HISI_SAS_BIST_CODE_MODE_TRAIN_DONE,
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HISI_SAS_BIST_CODE_MODE_HFTP,
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HISI_SAS_BIST_CODE_MODE_MFTP,
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HISI_SAS_BIST_CODE_MODE_LFTP,
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HISI_SAS_BIST_CODE_MODE_FIXED_DATA,
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};
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struct hisi_sas_hw {
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int (*hw_init)(struct hisi_hba *hisi_hba);
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int (*interrupt_preinit)(struct hisi_hba *hisi_hba);
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void (*setup_itct)(struct hisi_hba *hisi_hba,
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struct hisi_sas_device *device);
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int (*slot_index_alloc)(struct hisi_hba *hisi_hba,
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struct domain_device *device);
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struct hisi_sas_device *(*alloc_dev)(struct domain_device *device);
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void (*sl_notify_ssp)(struct hisi_hba *hisi_hba, int phy_no);
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void (*start_delivery)(struct hisi_sas_dq *dq);
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void (*prep_ssp)(struct hisi_hba *hisi_hba,
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struct hisi_sas_slot *slot);
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void (*prep_smp)(struct hisi_hba *hisi_hba,
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struct hisi_sas_slot *slot);
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void (*prep_stp)(struct hisi_hba *hisi_hba,
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struct hisi_sas_slot *slot);
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void (*prep_abort)(struct hisi_hba *hisi_hba,
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struct hisi_sas_slot *slot);
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void (*phys_init)(struct hisi_hba *hisi_hba);
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void (*phy_start)(struct hisi_hba *hisi_hba, int phy_no);
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void (*phy_disable)(struct hisi_hba *hisi_hba, int phy_no);
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void (*phy_hard_reset)(struct hisi_hba *hisi_hba, int phy_no);
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void (*get_events)(struct hisi_hba *hisi_hba, int phy_no);
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void (*phy_set_linkrate)(struct hisi_hba *hisi_hba, int phy_no,
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struct sas_phy_linkrates *linkrates);
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enum sas_linkrate (*phy_get_max_linkrate)(void);
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int (*clear_itct)(struct hisi_hba *hisi_hba,
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struct hisi_sas_device *dev);
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void (*free_device)(struct hisi_sas_device *sas_dev);
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int (*get_wideport_bitmap)(struct hisi_hba *hisi_hba, int port_id);
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void (*dereg_device)(struct hisi_hba *hisi_hba,
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struct domain_device *device);
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int (*soft_reset)(struct hisi_hba *hisi_hba);
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u32 (*get_phys_state)(struct hisi_hba *hisi_hba);
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int (*write_gpio)(struct hisi_hba *hisi_hba, u8 reg_type,
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u8 reg_index, u8 reg_count, u8 *write_data);
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void (*wait_cmds_complete_timeout)(struct hisi_hba *hisi_hba,
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int delay_ms, int timeout_ms);
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int (*debugfs_snapshot_regs)(struct hisi_hba *hisi_hba);
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int complete_hdr_size;
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const struct scsi_host_template *sht;
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};
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#define HISI_SAS_MAX_DEBUGFS_DUMP (50)
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struct hisi_sas_debugfs_cq {
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struct hisi_sas_cq *cq;
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void *complete_hdr;
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};
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struct hisi_sas_debugfs_dq {
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struct hisi_sas_dq *dq;
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struct hisi_sas_cmd_hdr *hdr;
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};
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struct hisi_sas_debugfs_regs {
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struct hisi_hba *hisi_hba;
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u32 *data;
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};
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struct hisi_sas_debugfs_port {
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struct hisi_sas_phy *phy;
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u32 *data;
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};
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struct hisi_sas_debugfs_iost {
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struct hisi_sas_iost *iost;
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};
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struct hisi_sas_debugfs_itct {
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struct hisi_sas_itct *itct;
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};
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struct hisi_sas_debugfs_iost_cache {
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struct hisi_sas_iost_itct_cache *cache;
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};
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struct hisi_sas_debugfs_itct_cache {
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struct hisi_sas_iost_itct_cache *cache;
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};
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struct hisi_hba {
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/* This must be the first element, used by SHOST_TO_SAS_HA */
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struct sas_ha_struct *p;
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struct platform_device *platform_dev;
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struct pci_dev *pci_dev;
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struct device *dev;
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int prot_mask;
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void __iomem *regs;
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void __iomem *sgpio_regs;
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struct regmap *ctrl;
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u32 ctrl_reset_reg;
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u32 ctrl_reset_sts_reg;
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u32 ctrl_clock_ena_reg;
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u32 refclk_frequency_mhz;
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u8 sas_addr[SAS_ADDR_SIZE];
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int *irq_map; /* v2 hw */
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int n_phy;
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spinlock_t lock;
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struct semaphore sem;
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struct timer_list timer;
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struct workqueue_struct *wq;
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int slot_index_count;
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int last_slot_index;
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int last_dev_id;
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unsigned long *slot_index_tags;
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unsigned long reject_stp_links_msk;
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/* SCSI/SAS glue */
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struct sas_ha_struct sha;
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struct Scsi_Host *shost;
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struct hisi_sas_cq cq[HISI_SAS_MAX_QUEUES];
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struct hisi_sas_dq dq[HISI_SAS_MAX_QUEUES];
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struct hisi_sas_phy phy[HISI_SAS_MAX_PHYS];
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struct hisi_sas_port port[HISI_SAS_MAX_PHYS];
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|
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int queue_count;
|
|
|
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struct hisi_sas_device devices[HISI_SAS_MAX_DEVICES];
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struct hisi_sas_cmd_hdr *cmd_hdr[HISI_SAS_MAX_QUEUES];
|
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dma_addr_t cmd_hdr_dma[HISI_SAS_MAX_QUEUES];
|
|
void *complete_hdr[HISI_SAS_MAX_QUEUES];
|
|
dma_addr_t complete_hdr_dma[HISI_SAS_MAX_QUEUES];
|
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struct hisi_sas_initial_fis *initial_fis;
|
|
dma_addr_t initial_fis_dma;
|
|
struct hisi_sas_itct *itct;
|
|
dma_addr_t itct_dma;
|
|
struct hisi_sas_iost *iost;
|
|
dma_addr_t iost_dma;
|
|
struct hisi_sas_breakpoint *breakpoint;
|
|
dma_addr_t breakpoint_dma;
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struct hisi_sas_breakpoint *sata_breakpoint;
|
|
dma_addr_t sata_breakpoint_dma;
|
|
struct hisi_sas_slot *slot_info;
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|
unsigned long flags;
|
|
const struct hisi_sas_hw *hw; /* Low level hw interface */
|
|
unsigned long sata_dev_bitmap[BITS_TO_LONGS(HISI_SAS_MAX_DEVICES)];
|
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struct work_struct rst_work;
|
|
u32 phy_state;
|
|
u32 intr_coal_ticks; /* Time of interrupt coalesce in us */
|
|
u32 intr_coal_count; /* Interrupt count to coalesce */
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|
|
|
int cq_nvecs;
|
|
|
|
/* bist */
|
|
enum sas_linkrate debugfs_bist_linkrate;
|
|
int debugfs_bist_code_mode;
|
|
int debugfs_bist_phy_no;
|
|
int debugfs_bist_mode;
|
|
u32 debugfs_bist_cnt;
|
|
int debugfs_bist_enable;
|
|
u32 debugfs_bist_ffe[HISI_SAS_MAX_PHYS][FFE_CFG_MAX];
|
|
u32 debugfs_bist_fixed_code[FIXED_CODE_MAX];
|
|
|
|
/* debugfs memories */
|
|
/* Put Global AXI and RAS Register into register array */
|
|
struct hisi_sas_debugfs_regs debugfs_regs[HISI_SAS_MAX_DEBUGFS_DUMP][DEBUGFS_REGS_NUM];
|
|
struct hisi_sas_debugfs_port debugfs_port_reg[HISI_SAS_MAX_DEBUGFS_DUMP][HISI_SAS_MAX_PHYS];
|
|
struct hisi_sas_debugfs_cq debugfs_cq[HISI_SAS_MAX_DEBUGFS_DUMP][HISI_SAS_MAX_QUEUES];
|
|
struct hisi_sas_debugfs_dq debugfs_dq[HISI_SAS_MAX_DEBUGFS_DUMP][HISI_SAS_MAX_QUEUES];
|
|
struct hisi_sas_debugfs_iost debugfs_iost[HISI_SAS_MAX_DEBUGFS_DUMP];
|
|
struct hisi_sas_debugfs_itct debugfs_itct[HISI_SAS_MAX_DEBUGFS_DUMP];
|
|
struct hisi_sas_debugfs_iost_cache debugfs_iost_cache[HISI_SAS_MAX_DEBUGFS_DUMP];
|
|
struct hisi_sas_debugfs_itct_cache debugfs_itct_cache[HISI_SAS_MAX_DEBUGFS_DUMP];
|
|
|
|
u64 debugfs_timestamp[HISI_SAS_MAX_DEBUGFS_DUMP];
|
|
int debugfs_dump_index;
|
|
struct dentry *debugfs_dir;
|
|
struct dentry *debugfs_dump_dentry;
|
|
struct dentry *debugfs_bist_dentry;
|
|
struct dentry *debugfs_fifo_dentry;
|
|
|
|
int iopoll_q_cnt;
|
|
};
|
|
|
|
/* Generic HW DMA host memory structures */
|
|
/* Delivery queue header */
|
|
struct hisi_sas_cmd_hdr {
|
|
/* dw0 */
|
|
__le32 dw0;
|
|
|
|
/* dw1 */
|
|
__le32 dw1;
|
|
|
|
/* dw2 */
|
|
__le32 dw2;
|
|
|
|
/* dw3 */
|
|
__le32 transfer_tags;
|
|
|
|
/* dw4 */
|
|
__le32 data_transfer_len;
|
|
|
|
/* dw5 */
|
|
__le32 first_burst_num;
|
|
|
|
/* dw6 */
|
|
__le32 sg_len;
|
|
|
|
/* dw7 */
|
|
__le32 dw7;
|
|
|
|
/* dw8-9 */
|
|
__le64 cmd_table_addr;
|
|
|
|
/* dw10-11 */
|
|
__le64 sts_buffer_addr;
|
|
|
|
/* dw12-13 */
|
|
__le64 prd_table_addr;
|
|
|
|
/* dw14-15 */
|
|
__le64 dif_prd_table_addr;
|
|
};
|
|
|
|
struct hisi_sas_itct {
|
|
__le64 qw0;
|
|
__le64 sas_addr;
|
|
__le64 qw2;
|
|
__le64 qw3;
|
|
__le64 qw4_15[12];
|
|
};
|
|
|
|
struct hisi_sas_iost {
|
|
__le64 qw0;
|
|
__le64 qw1;
|
|
__le64 qw2;
|
|
__le64 qw3;
|
|
};
|
|
|
|
struct hisi_sas_err_record {
|
|
u32 data[4];
|
|
};
|
|
|
|
struct hisi_sas_initial_fis {
|
|
struct hisi_sas_err_record err_record;
|
|
struct dev_to_host_fis fis;
|
|
u32 rsvd[3];
|
|
};
|
|
|
|
struct hisi_sas_breakpoint {
|
|
u8 data[128];
|
|
};
|
|
|
|
struct hisi_sas_sata_breakpoint {
|
|
struct hisi_sas_breakpoint tag[32];
|
|
};
|
|
|
|
struct hisi_sas_sge {
|
|
__le64 addr;
|
|
__le32 page_ctrl_0;
|
|
__le32 page_ctrl_1;
|
|
__le32 data_len;
|
|
__le32 data_off;
|
|
};
|
|
|
|
struct hisi_sas_command_table_smp {
|
|
u8 bytes[44];
|
|
};
|
|
|
|
struct hisi_sas_command_table_stp {
|
|
struct host_to_dev_fis command_fis;
|
|
u8 dummy[12];
|
|
u8 atapi_cdb[ATAPI_CDB_LEN];
|
|
};
|
|
|
|
#define HISI_SAS_SGE_PAGE_CNT (124)
|
|
struct hisi_sas_sge_page {
|
|
struct hisi_sas_sge sge[HISI_SAS_SGE_PAGE_CNT];
|
|
} __aligned(16);
|
|
|
|
#define HISI_SAS_SGE_DIF_PAGE_CNT HISI_SAS_SGE_PAGE_CNT
|
|
struct hisi_sas_sge_dif_page {
|
|
struct hisi_sas_sge sge[HISI_SAS_SGE_DIF_PAGE_CNT];
|
|
} __aligned(16);
|
|
|
|
struct hisi_sas_command_table_ssp {
|
|
struct ssp_frame_hdr hdr;
|
|
union {
|
|
struct {
|
|
struct ssp_command_iu task;
|
|
u32 prot[7];
|
|
};
|
|
struct ssp_tmf_iu ssp_task;
|
|
struct xfer_rdy_iu xfer_rdy;
|
|
struct ssp_response_iu ssp_res;
|
|
} u;
|
|
};
|
|
|
|
union hisi_sas_command_table {
|
|
struct hisi_sas_command_table_ssp ssp;
|
|
struct hisi_sas_command_table_smp smp;
|
|
struct hisi_sas_command_table_stp stp;
|
|
} __aligned(16);
|
|
|
|
struct hisi_sas_status_buffer {
|
|
struct hisi_sas_err_record err;
|
|
u8 iu[1024];
|
|
} __aligned(16);
|
|
|
|
struct hisi_sas_slot_buf_table {
|
|
struct hisi_sas_status_buffer status_buffer;
|
|
union hisi_sas_command_table command_header;
|
|
struct hisi_sas_sge_page sge_page;
|
|
};
|
|
|
|
struct hisi_sas_slot_dif_buf_table {
|
|
struct hisi_sas_slot_buf_table slot_buf;
|
|
struct hisi_sas_sge_dif_page sge_dif_page;
|
|
};
|
|
|
|
extern struct scsi_transport_template *hisi_sas_stt;
|
|
|
|
extern bool hisi_sas_debugfs_enable;
|
|
extern u32 hisi_sas_debugfs_dump_count;
|
|
extern struct dentry *hisi_sas_debugfs_dir;
|
|
|
|
extern void hisi_sas_stop_phys(struct hisi_hba *hisi_hba);
|
|
extern int hisi_sas_alloc(struct hisi_hba *hisi_hba);
|
|
extern void hisi_sas_free(struct hisi_hba *hisi_hba);
|
|
extern u8 hisi_sas_get_ata_protocol(struct host_to_dev_fis *fis,
|
|
int direction);
|
|
extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port);
|
|
extern void hisi_sas_sata_done(struct sas_task *task,
|
|
struct hisi_sas_slot *slot);
|
|
extern int hisi_sas_get_fw_info(struct hisi_hba *hisi_hba);
|
|
extern int hisi_sas_probe(struct platform_device *pdev,
|
|
const struct hisi_sas_hw *ops);
|
|
extern void hisi_sas_remove(struct platform_device *pdev);
|
|
|
|
extern int hisi_sas_slave_configure(struct scsi_device *sdev);
|
|
extern int hisi_sas_slave_alloc(struct scsi_device *sdev);
|
|
extern int hisi_sas_scan_finished(struct Scsi_Host *shost, unsigned long time);
|
|
extern void hisi_sas_scan_start(struct Scsi_Host *shost);
|
|
extern int hisi_sas_host_reset(struct Scsi_Host *shost, int reset_type);
|
|
extern void hisi_sas_phy_enable(struct hisi_hba *hisi_hba, int phy_no,
|
|
int enable);
|
|
extern void hisi_sas_phy_down(struct hisi_hba *hisi_hba, int phy_no, int rdy,
|
|
gfp_t gfp_flags);
|
|
extern void hisi_sas_phy_bcast(struct hisi_sas_phy *phy);
|
|
extern void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba,
|
|
struct sas_task *task,
|
|
struct hisi_sas_slot *slot,
|
|
bool need_lock);
|
|
extern void hisi_sas_init_mem(struct hisi_hba *hisi_hba);
|
|
extern void hisi_sas_rst_work_handler(struct work_struct *work);
|
|
extern void hisi_sas_sync_rst_work_handler(struct work_struct *work);
|
|
extern void hisi_sas_phy_oob_ready(struct hisi_hba *hisi_hba, int phy_no);
|
|
extern bool hisi_sas_notify_phy_event(struct hisi_sas_phy *phy,
|
|
enum hisi_sas_phy_event event);
|
|
extern void hisi_sas_release_tasks(struct hisi_hba *hisi_hba);
|
|
extern u8 hisi_sas_get_prog_phy_linkrate_mask(enum sas_linkrate max);
|
|
extern void hisi_sas_sync_cqs(struct hisi_hba *hisi_hba);
|
|
extern void hisi_sas_sync_poll_cqs(struct hisi_hba *hisi_hba);
|
|
extern void hisi_sas_controller_reset_prepare(struct hisi_hba *hisi_hba);
|
|
extern void hisi_sas_controller_reset_done(struct hisi_hba *hisi_hba);
|
|
#endif
|