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d610b54f77
The mpll clock is a kind of fractional divider which can gate. When the RW operation have been added, enable/disable ops have been mistakenly inserted in this driver. These ops are essentially a poor copy/paste of the generic gate ops. This change removes the gate ops from the mpll driver and inserts a generic gate clock on each mpll divider, simplifying the mpll driver and reducing code duplication. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
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| .. | ||
| axg.c | ||
| axg.h | ||
| clk-audio-divider.c | ||
| clk-cpu.c | ||
| clk-mpll.c | ||
| clk-pll.c | ||
| clk-regmap.c | ||
| clk-regmap.h | ||
| clkc.h | ||
| gxbb-aoclk-32k.c | ||
| gxbb-aoclk.c | ||
| gxbb-aoclk.h | ||
| gxbb.c | ||
| gxbb.h | ||
| Kconfig | ||
| Makefile | ||
| meson8b.c | ||
| meson8b.h | ||