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d5c7cc28aa
Following addition of cascaded s_stream call within mipid02_stream_enable and mipid02_stream_disable, the mipid02_stream_enable error handling must be fixed to simply disable the clocks & data lanes without also calling again the s_stream of the source subdev. Moreover, main control registers are reset to 0 for all cases of error within the mipid02_stream_enable even if they haven't yet been written. Correct this behavior by simply returning an error when register clear are not necessary. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl> |
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cec | ||
common | ||
dvb-core | ||
dvb-frontends | ||
firewire | ||
i2c | ||
mc | ||
mmc | ||
pci | ||
platform | ||
radio | ||
rc | ||
spi | ||
test-drivers | ||
tuners | ||
usb | ||
v4l2-core | ||
Kconfig | ||
Makefile |