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2bc3fc877a
Right now the RISC-V timer driver is convoluted to support: 1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR for clocksource and SBI timer calls for clockevent device. 2. Linux RISC-V M-mode (without MMU) where it will use CLINT MMIO counter register for clocksource and CLINT MMIO compare register for clockevent device. We now have a separate CLINT timer driver which also provide CLINT based IPI operations so let's remove CLINT MMIO related code from arch/riscv directory and RISC-V timer driver. Signed-off-by: Anup Patel <anup.patel@wdc.com> Tested-by: Emil Renner Berhing <kernel@esmil.dk> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
115 lines
2.4 KiB
C
115 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
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* Chen Liqin <liqin.chen@sunplusct.com>
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* Lennox Wu <lennox.wu@sunplusct.com>
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* Copyright (C) 2012 Regents of the University of California
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*/
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/memblock.h>
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#include <linux/sched.h>
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#include <linux/console.h>
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#include <linux/screen_info.h>
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#include <linux/of_fdt.h>
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#include <linux/of_platform.h>
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#include <linux/sched/task.h>
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#include <linux/swiotlb.h>
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#include <linux/smp.h>
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#include <asm/cpu_ops.h>
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#include <asm/setup.h>
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#include <asm/sections.h>
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#include <asm/sbi.h>
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#include <asm/tlbflush.h>
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#include <asm/thread_info.h>
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#include <asm/kasan.h>
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#include "head.h"
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#ifdef CONFIG_DUMMY_CONSOLE
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struct screen_info screen_info = {
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.orig_video_lines = 30,
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.orig_video_cols = 80,
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.orig_video_mode = 0,
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.orig_video_ega_bx = 0,
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.orig_video_isVGA = 1,
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.orig_video_points = 8
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};
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#endif
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/*
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* The lucky hart to first increment this variable will boot the other cores.
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* This is used before the kernel initializes the BSS so it can't be in the
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* BSS.
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*/
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atomic_t hart_lottery __section(.sdata);
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unsigned long boot_cpu_hartid;
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static DEFINE_PER_CPU(struct cpu, cpu_devices);
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void __init parse_dtb(void)
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{
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if (early_init_dt_scan(dtb_early_va))
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return;
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pr_err("No DTB passed to the kernel\n");
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#ifdef CONFIG_CMDLINE_FORCE
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strlcpy(boot_command_line, CONFIG_CMDLINE, COMMAND_LINE_SIZE);
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pr_info("Forcing kernel command line to: %s\n", boot_command_line);
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#endif
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}
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void __init setup_arch(char **cmdline_p)
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{
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init_mm.start_code = (unsigned long) _stext;
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init_mm.end_code = (unsigned long) _etext;
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init_mm.end_data = (unsigned long) _edata;
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init_mm.brk = (unsigned long) _end;
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*cmdline_p = boot_command_line;
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parse_early_param();
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setup_bootmem();
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paging_init();
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#if IS_ENABLED(CONFIG_BUILTIN_DTB)
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unflatten_and_copy_device_tree();
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#else
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unflatten_device_tree();
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#endif
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#ifdef CONFIG_SWIOTLB
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swiotlb_init(1);
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#endif
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#ifdef CONFIG_KASAN
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kasan_init();
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#endif
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#if IS_ENABLED(CONFIG_RISCV_SBI)
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sbi_init();
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#endif
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#ifdef CONFIG_SMP
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setup_smp();
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#endif
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riscv_fill_hwcap();
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}
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static int __init topology_init(void)
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{
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int i;
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for_each_possible_cpu(i) {
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struct cpu *cpu = &per_cpu(cpu_devices, i);
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cpu->hotpluggable = cpu_has_hotplug(i);
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register_cpu(cpu, i);
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}
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return 0;
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}
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subsys_initcall(topology_init);
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