linux/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
Rob Herring 3c75ce7cc3 dt-bindings: Drop type from 'cpus' property
'cpus' is a common property, and it is now defined in dtschema schemas,
so drop the type references in the tree.

Acked-by: Suzuki K Poulose <suzuki.poulse@arm.com>
Acked-by: Bjorn Andersson <andersson@kernel.org>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20221111212857.4104308-1-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
2022-12-06 14:50:35 -06:00

45 lines
1.2 KiB
YAML

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2021 Arm Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
maintainers:
- Suzuki K Poulose <suzuki.poulose@arm.com>
- Robin Murphy <robin.murphy@arm.com>
description:
ARM DynamIQ Shared Unit (DSU) integrates one or more CPU cores with a shared
L3 memory system, control logic and external interfaces to form a multicore
cluster. The PMU enables gathering various statistics on the operation of the
DSU. The PMU provides independent 32-bit counters that can count any of the
supported events, along with a 64-bit cycle counter. The PMU is accessed via
CPU system registers and has no MMIO component.
properties:
compatible:
oneOf:
- const: arm,dsu-pmu
- items:
- const: arm,dsu-110-pmu
- const: arm,dsu-pmu
interrupts:
items:
- description: nCLUSTERPMUIRQ interrupt
cpus:
minItems: 1
maxItems: 12
description: List of phandles for the CPUs connected to this DSU instance.
required:
- compatible
- interrupts
- cpus
additionalProperties: false