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SPI and I2C bus node names are expected to be "spi" or "i2c", respectively, with nothing else, a unit-address, or a '-N' index. A pattern of 'spi0' or 'i2c0' or similar has crept in. Fix all these cases. Mostly scripted with the following commands: git grep -l '\si2c[0-9] {' Documentation/devicetree/ | xargs sed -i -e 's/i2c[0-9] {/i2c {/' git grep -l '\sspi[0-9] {' Documentation/devicetree/ | xargs sed -i -e 's/spi[0-9] {/spi {/' With this, a few errors in examples were exposed and fixed. Acked-by: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> # for the microchip,mcp251xfd.yaml Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com> # for power-supply Acked-by: Wolfram Sang <wsa@kernel.org> Acked-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/20230228215433.3944508-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
210 lines
4.7 KiB
YAML
210 lines
4.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/ti,lmk04832.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Texas Instruments LMK04832 Clock Controller
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maintainers:
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- Liam Beguin <liambeguin@gmail.com>
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description: |
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Devicetree binding for the LMK04832, a clock conditioner with JEDEC JESD204B
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support. The LMK04832 is pin compatible with the LMK0482x family.
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Link to datasheet, https://www.ti.com/lit/ds/symlink/lmk04832.pdf
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properties:
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compatible:
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enum:
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- ti,lmk04832
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reg:
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maxItems: 1
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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'#clock-cells':
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const: 1
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spi-max-frequency:
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maximum: 5000000
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clocks:
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items:
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- description: PLL2 reference clock.
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clock-names:
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items:
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- const: oscin
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reset-gpios:
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maxItems: 1
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ti,spi-4wire-rdbk:
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description: |
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Select SPI 4wire readback pin configuration.
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Available readback pins are,
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CLKin_SEL0 0
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CLKin_SEL1 1
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RESET 2
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2]
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default: 1
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ti,vco-hz:
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description: Optional to set VCO frequency of the PLL in Hertz.
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ti,sysref-ddly:
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description: SYSREF digital delay value.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 8
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maximum: 8191
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default: 8
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ti,sysref-mux:
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description: |
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SYSREF Mux configuration.
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Available options are,
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Normal SYNC 0
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Re-clocked 1
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SYSREF Pulser 2
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SYSREF Continuous 3
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2, 3]
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default: 3
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ti,sync-mode:
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description: SYNC pin configuration.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2]
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default: 1
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ti,sysref-pulse-count:
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description:
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Number of SYSREF pulses to send when SYSREF is not in continuous mode.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [1, 2, 4, 8]
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default: 4
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patternProperties:
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"@[0-9a-d]+$":
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type: object
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description:
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Child nodes used to configure output clocks.
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properties:
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reg:
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description:
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clock output identifier.
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minimum: 0
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maximum: 13
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ti,clkout-fmt:
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description:
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Clock output format.
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Available options are,
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Powerdown 0x00
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LVDS 0x01
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HSDS 6 mA 0x02
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HSDS 8 mA 0x03
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LVPECL 1600 mV 0x04
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LVPECL 2000 mV 0x05
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LCPECL 0x06
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CML 16 mA 0x07
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CML 24 mA 0x08
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CML 32 mA 0x09
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CMOS (Off/Inverted) 0x0a
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CMOS (Normal/Off) 0x0b
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CMOS (Inverted/Inverted) 0x0c
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CMOS (Inverted/Normal) 0x0d
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CMOS (Normal/Inverted) 0x0e
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CMOS (Normal/Normal) 0x0f
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 15
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ti,clkout-sysref:
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description:
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Select SYSREF clock path for output clock.
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type: boolean
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required:
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- reg
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additionalProperties: false
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required:
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- compatible
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- reg
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- '#clock-cells'
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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clocks {
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lmk04832_oscin: oscin {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <122880000>;
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clock-output-names = "lmk04832-oscin";
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};
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};
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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lmk04832: clock-controller@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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compatible = "ti,lmk04832";
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spi-max-frequency = <781250>;
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reset-gpios = <&gpio_lmk 0 0 0>;
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#clock-cells = <1>;
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clocks = <&lmk04832_oscin>;
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clock-names = "oscin";
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ti,spi-4wire-rdbk = <0>;
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ti,vco-hz = <2457600000>;
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assigned-clocks =
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<&lmk04832 0>, <&lmk04832 1>,
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<&lmk04832 2>, <&lmk04832 3>,
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<&lmk04832 4>,
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<&lmk04832 6>, <&lmk04832 7>,
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<&lmk04832 10>, <&lmk04832 11>;
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assigned-clock-rates =
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<122880000>, <384000>,
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<122880000>, <384000>,
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<122880000>,
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<153600000>, <384000>,
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<614400000>, <384000>;
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clkout0@0 {
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reg = <0>;
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ti,clkout-fmt = <0x01>; // LVDS
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};
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clkout1@1 {
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reg = <1>;
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ti,clkout-fmt = <0x01>; // LVDS
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ti,clkout-sysref;
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};
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};
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};
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