linux/Documentation/devicetree/bindings/clock/qcom,gpucc-sdm660.yaml
Krzysztof Kozlowski ece3c31981 dt-bindings: clock: qcom: Clean-up titles and descriptions
Clean the Qualcomm SoCs clock bindings:
1. Drop redundant "bindings" in title.
2. Correct language grammar "<independent clause without verb>, which
   supports" -> "provides".
3. Use full path to the bindings header, so tools can validate it.
4. Drop quotes where not needed.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> # msm8998
Acked-by: Jeffrey Hugo <quic_jhugo@quicinc.com> # mmcc
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221102163153.55460-2-krzysztof.kozlowski@linaro.org
2022-11-07 22:47:27 -06:00

77 lines
1.7 KiB
YAML

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gpucc-sdm660.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on SDM630 and SDM660
maintainers:
- AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
description: |
Qualcomm graphics clock control module provides the clocks, resets and
power domains on SDM630 and SDM660.
See also dt-bindings/clock/qcom,gpucc-sdm660.h.
properties:
compatible:
enum:
- qcom,gpucc-sdm630
- qcom,gpucc-sdm660
clocks:
items:
- description: Board XO source
- description: GPLL0 main gpu branch
- description: GPLL0 divider gpu branch
clock-names:
items:
- const: xo
- const: gcc_gpu_gpll0_clk
- const: gcc_gpu_gpll0_div_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sdm660.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
clock-controller@5065000 {
compatible = "qcom,gpucc-sdm660";
reg = <0x05065000 0x9038>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_CLK>,
<&gcc GCC_GPU_GPLL0_DIV_CLK>;
clock-names = "xo", "gcc_gpu_gpll0_clk",
"gcc_gpu_gpll0_div_clk";
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
};
...