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a276e588a9
This patch unifies the sh3 external irq pin code. It buys us some savings with reduced code redundancy, but the main feature with this change is irq sense selection support for all sh3 processors. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
194 lines
5.2 KiB
C
194 lines
5.2 KiB
C
/*
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* SH3 Setup code for SH7706, SH7707, SH7708, SH7709
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*
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* Copyright (C) 2007 Magnus Damm
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*
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* Based on setup-sh7709.c
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*
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* Copyright (C) 2006 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/platform_device.h>
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#include <linux/serial.h>
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#include <linux/serial_sci.h>
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
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PINT07, PINT815,
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DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3,
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SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
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SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
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SCI_ERI, SCI_RXI, SCI_TXI, SCI_TEI,
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ADC_ADI,
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LCDC, PCC0, PCC1,
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TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
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RTC_ATI, RTC_PRI, RTC_CUI,
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WDT,
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REF_RCMI, REF_ROVI,
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/* interrupt groups */
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RTC, REF, TMU2, DMAC, SCI, SCIF2, SCIF0,
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
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INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
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INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
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INTC_VECT(RTC_CUI, 0x4c0),
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INTC_VECT(SCI_ERI, 0x4e0), INTC_VECT(SCI_RXI, 0x500),
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INTC_VECT(SCI_TXI, 0x520), INTC_VECT(SCI_TEI, 0x540),
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INTC_VECT(WDT, 0x560),
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INTC_VECT(REF_RCMI, 0x580),
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INTC_VECT(REF_ROVI, 0x5a0),
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#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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/* IRQ0->5 are handled in setup-sh3.c */
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INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820),
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INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860),
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INTC_VECT(ADC_ADI, 0x980),
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INTC_VECT(SCIF2_ERI, 0x900), INTC_VECT(SCIF2_RXI, 0x920),
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INTC_VECT(SCIF2_BRI, 0x940), INTC_VECT(SCIF2_TXI, 0x960),
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
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INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
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INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7707)
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INTC_VECT(LCDC, 0x9a0),
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INTC_VECT(PCC0, 0x9c0), INTC_VECT(PCC1, 0x9e0),
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#endif
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};
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
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INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
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INTC_GROUP(REF, REF_RCMI, REF_ROVI),
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INTC_GROUP(DMAC, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
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INTC_GROUP(SCI, SCI_ERI, SCI_RXI, SCI_TXI, SCI_TEI),
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INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
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INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
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};
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
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{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
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#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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{ 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
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{ 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
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{ 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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{ 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } },
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{ 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } },
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7707)
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{ 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
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#endif
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};
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static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, groups,
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NULL, prio_registers, NULL);
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static struct resource rtc_resources[] = {
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[0] = {
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.start = 0xfffffec0,
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.end = 0xfffffec0 + 0x1e,
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.flags = IORESOURCE_IO,
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},
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[1] = {
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.start = 21,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.start = 22,
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.flags = IORESOURCE_IRQ,
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},
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[3] = {
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.start = 20,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device rtc_device = {
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.name = "sh-rtc",
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.id = -1,
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.num_resources = ARRAY_SIZE(rtc_resources),
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.resource = rtc_resources,
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};
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static struct plat_sci_port sci_platform_data[] = {
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{
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.mapbase = 0xfffffe80,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCI,
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.irqs = { 23, 24, 25, 0 },
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},
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#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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{
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.mapbase = 0xa4000150,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 56, 57, 59, 58 },
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},
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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{
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.mapbase = 0xa4000140,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_IRDA,
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.irqs = { 52, 53, 55, 54 },
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},
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#endif
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{
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.flags = 0,
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}
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};
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static struct platform_device sci_device = {
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.name = "sh-sci",
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.id = -1,
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.dev = {
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.platform_data = sci_platform_data,
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},
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};
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static struct platform_device *sh770x_devices[] __initdata = {
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&sci_device,
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&rtc_device,
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};
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static int __init sh770x_devices_setup(void)
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{
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return platform_add_devices(sh770x_devices,
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ARRAY_SIZE(sh770x_devices));
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}
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__initcall(sh770x_devices_setup);
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void __init plat_irq_setup(void)
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{
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register_intc_controller(&intc_desc);
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#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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plat_irq_setup_sh3();
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#endif
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}
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