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0953fb2637
Now that entry code handles IRQ entry (including setting the IRQ regs)
before calling irqchip code, irqchip code can safely call
generic_handle_domain_irq(), and there's no functional reason for it to
call handle_domain_irq().
Let's cement this split of responsibility and remove handle_domain_irq()
entirely, updating irqchip drivers to call generic_handle_domain_irq().
For consistency, handle_domain_nmi() is similarly removed and replaced
with a generic_handle_domain_nmi() function which also does not perform
any entry logic.
Previously handle_domain_{irq,nmi}() had a WARN_ON() which would fire
when they were called in an inappropriate context. So that we can
identify similar issues going forward, similar WARN_ON_ONCE() logic is
added to the generic_handle_*() functions, and comments are updated for
clarity and consistency.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
240 lines
6.0 KiB
C
240 lines
6.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
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* Add Alphascale ASM9260 support.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/stmp_device.h>
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#include <asm/exception.h>
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#include "alphascale_asm9260-icoll.h"
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/*
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* this device provide 4 offsets for each register:
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* 0x0 - plain read write mode
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* 0x4 - set mode, OR logic.
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* 0x8 - clr mode, XOR logic.
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* 0xc - togle mode.
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*/
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#define SET_REG 4
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#define CLR_REG 8
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#define HW_ICOLL_VECTOR 0x0000
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#define HW_ICOLL_LEVELACK 0x0010
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#define HW_ICOLL_CTRL 0x0020
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#define HW_ICOLL_STAT_OFFSET 0x0070
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#define HW_ICOLL_INTERRUPT0 0x0120
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#define HW_ICOLL_INTERRUPTn(n) ((n) * 0x10)
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#define BM_ICOLL_INTR_ENABLE BIT(2)
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#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1
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#define ICOLL_NUM_IRQS 128
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enum icoll_type {
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ICOLL,
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ASM9260_ICOLL,
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};
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struct icoll_priv {
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void __iomem *vector;
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void __iomem *levelack;
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void __iomem *ctrl;
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void __iomem *stat;
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void __iomem *intr;
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void __iomem *clear;
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enum icoll_type type;
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};
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static struct icoll_priv icoll_priv;
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static struct irq_domain *icoll_domain;
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/* calculate bit offset depending on number of interrupt per register */
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static u32 icoll_intr_bitshift(struct irq_data *d, u32 bit)
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{
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/*
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* mask lower part of hwirq to convert it
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* in 0, 1, 2 or 3 and then multiply it by 8 (or shift by 3)
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*/
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return bit << ((d->hwirq & 3) << 3);
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}
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/* calculate mem offset depending on number of interrupt per register */
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static void __iomem *icoll_intr_reg(struct irq_data *d)
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{
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/* offset = hwirq / intr_per_reg * 0x10 */
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return icoll_priv.intr + ((d->hwirq >> 2) * 0x10);
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}
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static void icoll_ack_irq(struct irq_data *d)
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{
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/*
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* The Interrupt Collector is able to prioritize irqs.
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* Currently only level 0 is used. So acking can use
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* BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally.
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*/
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__raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0,
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icoll_priv.levelack);
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}
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static void icoll_mask_irq(struct irq_data *d)
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{
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__raw_writel(BM_ICOLL_INTR_ENABLE,
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icoll_priv.intr + CLR_REG + HW_ICOLL_INTERRUPTn(d->hwirq));
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}
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static void icoll_unmask_irq(struct irq_data *d)
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{
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__raw_writel(BM_ICOLL_INTR_ENABLE,
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icoll_priv.intr + SET_REG + HW_ICOLL_INTERRUPTn(d->hwirq));
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}
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static void asm9260_mask_irq(struct irq_data *d)
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{
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__raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE),
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icoll_intr_reg(d) + CLR_REG);
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}
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static void asm9260_unmask_irq(struct irq_data *d)
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{
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__raw_writel(ASM9260_BM_CLEAR_BIT(d->hwirq),
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icoll_priv.clear +
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ASM9260_HW_ICOLL_CLEARn(d->hwirq));
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__raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE),
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icoll_intr_reg(d) + SET_REG);
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}
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static struct irq_chip mxs_icoll_chip = {
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.irq_ack = icoll_ack_irq,
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.irq_mask = icoll_mask_irq,
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.irq_unmask = icoll_unmask_irq,
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.flags = IRQCHIP_MASK_ON_SUSPEND |
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IRQCHIP_SKIP_SET_WAKE,
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};
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static struct irq_chip asm9260_icoll_chip = {
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.irq_ack = icoll_ack_irq,
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.irq_mask = asm9260_mask_irq,
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.irq_unmask = asm9260_unmask_irq,
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.flags = IRQCHIP_MASK_ON_SUSPEND |
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IRQCHIP_SKIP_SET_WAKE,
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};
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asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
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{
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u32 irqnr;
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irqnr = __raw_readl(icoll_priv.stat);
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__raw_writel(irqnr, icoll_priv.vector);
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generic_handle_domain_irq(icoll_domain, irqnr);
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}
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static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct irq_chip *chip;
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if (icoll_priv.type == ICOLL)
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chip = &mxs_icoll_chip;
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else
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chip = &asm9260_icoll_chip;
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irq_set_chip_and_handler(virq, chip, handle_level_irq);
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return 0;
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}
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static const struct irq_domain_ops icoll_irq_domain_ops = {
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.map = icoll_irq_domain_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static void __init icoll_add_domain(struct device_node *np,
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int num)
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{
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icoll_domain = irq_domain_add_linear(np, num,
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&icoll_irq_domain_ops, NULL);
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if (!icoll_domain)
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panic("%pOF: unable to create irq domain", np);
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}
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static void __iomem * __init icoll_init_iobase(struct device_node *np)
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{
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void __iomem *icoll_base;
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icoll_base = of_io_request_and_map(np, 0, np->name);
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if (IS_ERR(icoll_base))
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panic("%pOF: unable to map resource", np);
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return icoll_base;
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}
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static int __init icoll_of_init(struct device_node *np,
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struct device_node *interrupt_parent)
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{
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void __iomem *icoll_base;
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icoll_priv.type = ICOLL;
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icoll_base = icoll_init_iobase(np);
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icoll_priv.vector = icoll_base + HW_ICOLL_VECTOR;
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icoll_priv.levelack = icoll_base + HW_ICOLL_LEVELACK;
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icoll_priv.ctrl = icoll_base + HW_ICOLL_CTRL;
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icoll_priv.stat = icoll_base + HW_ICOLL_STAT_OFFSET;
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icoll_priv.intr = icoll_base + HW_ICOLL_INTERRUPT0;
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icoll_priv.clear = NULL;
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/*
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* Interrupt Collector reset, which initializes the priority
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* for each irq to level 0.
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*/
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stmp_reset_block(icoll_priv.ctrl);
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icoll_add_domain(np, ICOLL_NUM_IRQS);
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return 0;
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}
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IRQCHIP_DECLARE(mxs, "fsl,icoll", icoll_of_init);
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static int __init asm9260_of_init(struct device_node *np,
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struct device_node *interrupt_parent)
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{
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void __iomem *icoll_base;
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int i;
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icoll_priv.type = ASM9260_ICOLL;
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icoll_base = icoll_init_iobase(np);
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icoll_priv.vector = icoll_base + ASM9260_HW_ICOLL_VECTOR;
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icoll_priv.levelack = icoll_base + ASM9260_HW_ICOLL_LEVELACK;
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icoll_priv.ctrl = icoll_base + ASM9260_HW_ICOLL_CTRL;
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icoll_priv.stat = icoll_base + ASM9260_HW_ICOLL_STAT_OFFSET;
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icoll_priv.intr = icoll_base + ASM9260_HW_ICOLL_INTERRUPT0;
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icoll_priv.clear = icoll_base + ASM9260_HW_ICOLL_CLEAR0;
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writel_relaxed(ASM9260_BM_CTRL_IRQ_ENABLE,
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icoll_priv.ctrl);
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/*
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* ASM9260 don't provide reset bit. So, we need to set level 0
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* manually.
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*/
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for (i = 0; i < 16 * 0x10; i += 0x10)
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writel(0, icoll_priv.intr + i);
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icoll_add_domain(np, ASM9260_NUM_IRQS);
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set_handle_irq(icoll_handle_irq);
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return 0;
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}
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IRQCHIP_DECLARE(asm9260, "alphascale,asm9260-icoll", asm9260_of_init);
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