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d552920a02
This is a power gating idle mode. It support power gating vdd_cpu rail after all cpu cores in "powered-down" status. For Tegra30, the CPU0 can enter this state only when all secondary CPU is offline. We need to take care and make sure whole secondary CPUs were offline and checking the CPU power gate status. After that, the CPU0 can go into "powered-down" state safely. Then shut off the CPU rail. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Base on the work by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
91 lines
2.4 KiB
C
91 lines
2.4 KiB
C
/*
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* Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __MACH_TEGRA_SLEEP_H
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#define __MACH_TEGRA_SLEEP_H
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#include "iomap.h"
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#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
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+ IO_CPU_VIRT)
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#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
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+ IO_PPSB_VIRT)
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#define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
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+ IO_PPSB_VIRT)
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#ifdef __ASSEMBLY__
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/* returns the offset of the flow controller halt register for a cpu */
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.macro cpu_to_halt_reg rd, rcpu
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cmp \rcpu, #0
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subne \rd, \rcpu, #1
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movne \rd, \rd, lsl #3
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addne \rd, \rd, #0x14
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moveq \rd, #0
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.endm
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/* returns the offset of the flow controller csr register for a cpu */
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.macro cpu_to_csr_reg rd, rcpu
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cmp \rcpu, #0
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subne \rd, \rcpu, #1
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movne \rd, \rd, lsl #3
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addne \rd, \rd, #0x18
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moveq \rd, #8
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.endm
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/* returns the ID of the current processor */
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.macro cpu_id, rd
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mrc p15, 0, \rd, c0, c0, 5
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and \rd, \rd, #0xF
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.endm
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/* loads a 32-bit value into a register without a data access */
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.macro mov32, reg, val
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movw \reg, #:lower16:\val
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movt \reg, #:upper16:\val
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.endm
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/* Macro to exit SMP coherency. */
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.macro exit_smp, tmp1, tmp2
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mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR
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bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW
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mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR
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isb
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cpu_id \tmp1
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mov \tmp1, \tmp1, lsl #2
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mov \tmp2, #0xf
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mov \tmp2, \tmp2, lsl \tmp1
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mov32 \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC
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str \tmp2, [\tmp1] @ invalidate SCU tags for CPU
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dsb
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.endm
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#else
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void tegra_resume(void);
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int tegra_sleep_cpu_finish(unsigned long);
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#ifdef CONFIG_HOTPLUG_CPU
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void tegra20_hotplug_init(void);
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void tegra30_hotplug_init(void);
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#else
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static inline void tegra20_hotplug_init(void) {}
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static inline void tegra30_hotplug_init(void) {}
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#endif
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int tegra30_sleep_cpu_secondary_finish(unsigned long);
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void tegra30_tear_down_cpu(void);
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#endif
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#endif
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