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3da1d7b1e0
'spear13xx_io_desc' is used only in this file. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Sachin Kamat <sachin.kamat@samsung.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
129 lines
3.2 KiB
C
129 lines
3.2 KiB
C
/*
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* arch/arm/mach-spear13xx/spear13xx.c
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*
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* SPEAr13XX machines common source file
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*
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* Copyright (C) 2012 ST Microelectronics
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* Viresh Kumar <viresh.linux@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#define pr_fmt(fmt) "SPEAr13xx: " fmt
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#include <linux/amba/pl022.h>
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#include <linux/clk.h>
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#include <linux/clocksource.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/map.h>
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#include <mach/spear.h>
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#include "generic.h"
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void __init spear13xx_l2x0_init(void)
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{
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/*
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* 512KB (64KB/way), 8-way associativity, parity supported
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*
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* FIXME: 9th bit, of Auxillary Controller register must be set
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* for some spear13xx devices for stable L2 operation.
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*
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* Enable Early BRESP, L2 prefetch for Instruction and Data,
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* write alloc and 'Full line of zero' options
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*
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*/
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if (!IS_ENABLED(CONFIG_CACHE_L2X0))
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return;
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writel_relaxed(0x06, VA_L2CC_BASE + L310_PREFETCH_CTRL);
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/*
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* Program following latencies in order to make
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* SPEAr1340 work at 600 MHz
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*/
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writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL);
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writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL);
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l2x0_init(VA_L2CC_BASE, 0x30a00001, 0xfe0fffff);
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}
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/*
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* Following will create 16MB static virtual/physical mappings
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* PHYSICAL VIRTUAL
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* 0xB3000000 0xFE000000
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* 0xE0000000 0xFD000000
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* 0xEC000000 0xFC000000
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* 0xED000000 0xFB000000
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*/
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static struct map_desc spear13xx_io_desc[] __initdata = {
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{
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.virtual = (unsigned long)VA_PERIP_GRP2_BASE,
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.pfn = __phys_to_pfn(PERIP_GRP2_BASE),
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.length = SZ_16M,
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.type = MT_DEVICE
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}, {
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.virtual = (unsigned long)VA_PERIP_GRP1_BASE,
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.pfn = __phys_to_pfn(PERIP_GRP1_BASE),
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.length = SZ_16M,
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.type = MT_DEVICE
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}, {
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.virtual = (unsigned long)VA_A9SM_AND_MPMC_BASE,
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.pfn = __phys_to_pfn(A9SM_AND_MPMC_BASE),
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.length = SZ_16M,
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.type = MT_DEVICE
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}, {
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.virtual = (unsigned long)VA_L2CC_BASE,
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.pfn = __phys_to_pfn(L2CC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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},
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};
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/* This will create static memory mapping for selected devices */
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void __init spear13xx_map_io(void)
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{
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iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc));
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}
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static void __init spear13xx_clk_init(void)
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{
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if (of_machine_is_compatible("st,spear1310"))
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spear1310_clk_init(VA_MISC_BASE, VA_SPEAR1310_RAS_BASE);
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else if (of_machine_is_compatible("st,spear1340"))
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spear1340_clk_init(VA_MISC_BASE);
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else
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pr_err("%s: Unknown machine\n", __func__);
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}
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void __init spear13xx_timer_init(void)
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{
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char pclk_name[] = "osc_24m_clk";
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struct clk *gpt_clk, *pclk;
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spear13xx_clk_init();
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/* get the system timer clock */
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gpt_clk = clk_get_sys("gpt0", NULL);
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if (IS_ERR(gpt_clk)) {
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pr_err("%s:couldn't get clk for gpt\n", __func__);
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BUG();
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}
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/* get the suitable parent clock for timer*/
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pclk = clk_get(NULL, pclk_name);
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if (IS_ERR(pclk)) {
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pr_err("%s:couldn't get %s as parent for gpt\n", __func__,
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pclk_name);
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BUG();
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}
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clk_set_parent(gpt_clk, pclk);
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clk_put(gpt_clk);
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clk_put(pclk);
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spear_setup_of_timer();
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clocksource_of_init();
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}
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