Archit Taneja d4cea38ebb drm/msm/dsi: Calculate link clock rates with updated dsi->lanes ... After the commit mentioned below, we start computing the byte and pixel clocks (dsi_calc_clk_rate) in the DSI bridge's mode_set() op. The calculation involves the number of DSI lanes being used by the downstream bridge/panel. If the downstream bridge/panel tries to change the number of DSI lanes (as done in the ADV7533 driver) in its mode_set() op, then our DSI host driver will not have the correct number of lanes when computing byte/pixel clocks. Fix this by delaying the clock rate calculation in the DSI bridge enable path. In particular, compute the clock rates in msm_dsi_host_get_phy_clk_req(). This fixes the DSI host error interrupts seen when we try to switch between modes that require different number of lanes (4 to 3 lanes, or vice versa) on db410c. The error interrupts occur since the byte/pixel clock rates aren't according to what the DSI video mode timing engine expects. Fixes: b62aa70a98 ("drm/msm/dsi: Move PHY operations out of host") Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>		2017-08-01 16:26:01 -04:00
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drm	drm/msm/dsi: Calculate link clock rates with updated dsi->lanes	2017-08-01 16:26:01 -04:00
host1x	gpu: host1x: Free the IOMMU domain when there is no device to attach	2017-07-27 16:57:34 +02:00
ipu-v3	Linux 4.12-rc5	2017-06-16 13:58:27 +10:00
vga	sched/wait: Rename wait_queue_t => wait_queue_entry_t	2017-06-20 12:18:27 +02:00
Makefile