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99306dfc06
Pull x86 timer updates from Thomas Gleixner: "These updates are related to TSC handling: - Support platforms which have synchronized TSCs but the boot CPU has a non zero TSC_ADJUST value, which is considered a firmware bug on normal systems. This applies to HPE/SGI UV platforms where the platform firmware uses TSC_ADJUST to ensure TSC synchronization across a huge number of sockets, but due to power on timings the boot CPU cannot be guaranteed to have a zero TSC_ADJUST register value. - Fix the ordering of udelay calibration and kvmclock_init() - Cleanup the udelay and calibration code" * 'x86-timers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/tsc: Mark cyc2ns_init() and detect_art() __init x86/platform/UV: Mark tsc_check_sync as an init function x86/tsc: Make CONFIG_X86_TSC=n build work again x86/platform/UV: Add check of TSC state set by UV BIOS x86/tsc: Provide a means to disable TSC ART x86/tsc: Drastically reduce the number of firmware bug warnings x86/tsc: Skip TSC test and error messages if already unstable x86/tsc: Add option that TSC on Socket 0 being non-zero is valid x86/timers: Move simple_udelay_calibration() past kvmclock_init() x86/timers: Make recalibrate_cpu_khz() void x86/timers: Move the simple udelay calibration to tsc.h
495 lines
13 KiB
C
495 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* check TSC synchronization.
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*
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* Copyright (C) 2006, Red Hat, Inc., Ingo Molnar
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*
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* We check whether all boot CPUs have their TSC's synchronized,
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* print a warning if not and turn off the TSC clock-source.
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*
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* The warp-check is point-to-point between two CPUs, the CPU
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* initiating the bootup is the 'source CPU', the freshly booting
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* CPU is the 'target CPU'.
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*
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* Only two CPUs may participate - they can enter in any order.
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* ( The serial nature of the boot logic and the CPU hotplug lock
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* protects against more than 2 CPUs entering this code. )
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*/
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#include <linux/topology.h>
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#include <linux/spinlock.h>
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#include <linux/kernel.h>
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#include <linux/smp.h>
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#include <linux/nmi.h>
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#include <asm/tsc.h>
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struct tsc_adjust {
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s64 bootval;
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s64 adjusted;
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unsigned long nextcheck;
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bool warned;
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};
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static DEFINE_PER_CPU(struct tsc_adjust, tsc_adjust);
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/*
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* TSC's on different sockets may be reset asynchronously.
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* This may cause the TSC ADJUST value on socket 0 to be NOT 0.
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*/
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bool __read_mostly tsc_async_resets;
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void mark_tsc_async_resets(char *reason)
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{
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if (tsc_async_resets)
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return;
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tsc_async_resets = true;
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pr_info("tsc: Marking TSC async resets true due to %s\n", reason);
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}
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void tsc_verify_tsc_adjust(bool resume)
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{
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struct tsc_adjust *adj = this_cpu_ptr(&tsc_adjust);
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s64 curval;
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if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
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return;
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/* Skip unnecessary error messages if TSC already unstable */
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if (check_tsc_unstable())
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return;
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/* Rate limit the MSR check */
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if (!resume && time_before(jiffies, adj->nextcheck))
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return;
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adj->nextcheck = jiffies + HZ;
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rdmsrl(MSR_IA32_TSC_ADJUST, curval);
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if (adj->adjusted == curval)
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return;
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/* Restore the original value */
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wrmsrl(MSR_IA32_TSC_ADJUST, adj->adjusted);
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if (!adj->warned || resume) {
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pr_warn(FW_BUG "TSC ADJUST differs: CPU%u %lld --> %lld. Restoring\n",
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smp_processor_id(), adj->adjusted, curval);
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adj->warned = true;
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}
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}
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static void tsc_sanitize_first_cpu(struct tsc_adjust *cur, s64 bootval,
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unsigned int cpu, bool bootcpu)
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{
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/*
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* First online CPU in a package stores the boot value in the
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* adjustment value. This value might change later via the sync
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* mechanism. If that fails we still can yell about boot values not
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* being consistent.
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*
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* On the boot cpu we just force set the ADJUST value to 0 if it's
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* non zero. We don't do that on non boot cpus because physical
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* hotplug should have set the ADJUST register to a value > 0 so
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* the TSC is in sync with the already running cpus.
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*
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* Also don't force the ADJUST value to zero if that is a valid value
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* for socket 0 as determined by the system arch. This is required
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* when multiple sockets are reset asynchronously with each other
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* and socket 0 may not have an TSC ADJUST value of 0.
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*/
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if (bootcpu && bootval != 0) {
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if (likely(!tsc_async_resets)) {
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pr_warn(FW_BUG "TSC ADJUST: CPU%u: %lld force to 0\n",
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cpu, bootval);
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wrmsrl(MSR_IA32_TSC_ADJUST, 0);
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bootval = 0;
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} else {
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pr_info("TSC ADJUST: CPU%u: %lld NOT forced to 0\n",
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cpu, bootval);
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}
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}
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cur->adjusted = bootval;
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}
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#ifndef CONFIG_SMP
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bool __init tsc_store_and_check_tsc_adjust(bool bootcpu)
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{
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struct tsc_adjust *cur = this_cpu_ptr(&tsc_adjust);
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s64 bootval;
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if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
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return false;
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/* Skip unnecessary error messages if TSC already unstable */
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if (check_tsc_unstable())
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return false;
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rdmsrl(MSR_IA32_TSC_ADJUST, bootval);
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cur->bootval = bootval;
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cur->nextcheck = jiffies + HZ;
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tsc_sanitize_first_cpu(cur, bootval, smp_processor_id(), bootcpu);
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return false;
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}
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#else /* !CONFIG_SMP */
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/*
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* Store and check the TSC ADJUST MSR if available
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*/
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bool tsc_store_and_check_tsc_adjust(bool bootcpu)
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{
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struct tsc_adjust *ref, *cur = this_cpu_ptr(&tsc_adjust);
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unsigned int refcpu, cpu = smp_processor_id();
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struct cpumask *mask;
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s64 bootval;
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if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
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return false;
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rdmsrl(MSR_IA32_TSC_ADJUST, bootval);
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cur->bootval = bootval;
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cur->nextcheck = jiffies + HZ;
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cur->warned = false;
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/*
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* If a non-zero TSC value for socket 0 may be valid then the default
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* adjusted value cannot assumed to be zero either.
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*/
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if (tsc_async_resets)
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cur->adjusted = bootval;
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/*
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* Check whether this CPU is the first in a package to come up. In
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* this case do not check the boot value against another package
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* because the new package might have been physically hotplugged,
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* where TSC_ADJUST is expected to be different. When called on the
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* boot CPU topology_core_cpumask() might not be available yet.
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*/
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mask = topology_core_cpumask(cpu);
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refcpu = mask ? cpumask_any_but(mask, cpu) : nr_cpu_ids;
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if (refcpu >= nr_cpu_ids) {
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tsc_sanitize_first_cpu(cur, bootval, smp_processor_id(),
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bootcpu);
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return false;
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}
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ref = per_cpu_ptr(&tsc_adjust, refcpu);
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/*
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* Compare the boot value and complain if it differs in the
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* package.
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*/
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if (bootval != ref->bootval)
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printk_once(FW_BUG "TSC ADJUST differs within socket(s), fixing all errors\n");
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/*
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* The TSC_ADJUST values in a package must be the same. If the boot
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* value on this newly upcoming CPU differs from the adjustment
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* value of the already online CPU in this package, set it to that
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* adjusted value.
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*/
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if (bootval != ref->adjusted) {
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cur->adjusted = ref->adjusted;
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wrmsrl(MSR_IA32_TSC_ADJUST, ref->adjusted);
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}
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/*
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* We have the TSCs forced to be in sync on this package. Skip sync
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* test:
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*/
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return true;
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}
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/*
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* Entry/exit counters that make sure that both CPUs
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* run the measurement code at once:
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*/
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static atomic_t start_count;
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static atomic_t stop_count;
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static atomic_t skip_test;
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static atomic_t test_runs;
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/*
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* We use a raw spinlock in this exceptional case, because
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* we want to have the fastest, inlined, non-debug version
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* of a critical section, to be able to prove TSC time-warps:
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*/
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static arch_spinlock_t sync_lock = __ARCH_SPIN_LOCK_UNLOCKED;
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static cycles_t last_tsc;
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static cycles_t max_warp;
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static int nr_warps;
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static int random_warps;
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/*
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* TSC-warp measurement loop running on both CPUs. This is not called
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* if there is no TSC.
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*/
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static cycles_t check_tsc_warp(unsigned int timeout)
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{
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cycles_t start, now, prev, end, cur_max_warp = 0;
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int i, cur_warps = 0;
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start = rdtsc_ordered();
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/*
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* The measurement runs for 'timeout' msecs:
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*/
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end = start + (cycles_t) tsc_khz * timeout;
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now = start;
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for (i = 0; ; i++) {
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/*
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* We take the global lock, measure TSC, save the
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* previous TSC that was measured (possibly on
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* another CPU) and update the previous TSC timestamp.
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*/
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arch_spin_lock(&sync_lock);
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prev = last_tsc;
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now = rdtsc_ordered();
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last_tsc = now;
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arch_spin_unlock(&sync_lock);
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/*
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* Be nice every now and then (and also check whether
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* measurement is done [we also insert a 10 million
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* loops safety exit, so we dont lock up in case the
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* TSC readout is totally broken]):
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*/
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if (unlikely(!(i & 7))) {
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if (now > end || i > 10000000)
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break;
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cpu_relax();
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touch_nmi_watchdog();
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}
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/*
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* Outside the critical section we can now see whether
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* we saw a time-warp of the TSC going backwards:
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*/
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if (unlikely(prev > now)) {
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arch_spin_lock(&sync_lock);
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max_warp = max(max_warp, prev - now);
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cur_max_warp = max_warp;
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/*
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* Check whether this bounces back and forth. Only
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* one CPU should observe time going backwards.
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*/
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if (cur_warps != nr_warps)
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random_warps++;
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nr_warps++;
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cur_warps = nr_warps;
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arch_spin_unlock(&sync_lock);
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}
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}
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WARN(!(now-start),
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"Warning: zero tsc calibration delta: %Ld [max: %Ld]\n",
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now-start, end-start);
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return cur_max_warp;
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}
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/*
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* If the target CPU coming online doesn't have any of its core-siblings
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* online, a timeout of 20msec will be used for the TSC-warp measurement
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* loop. Otherwise a smaller timeout of 2msec will be used, as we have some
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* information about this socket already (and this information grows as we
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* have more and more logical-siblings in that socket).
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*
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* Ideally we should be able to skip the TSC sync check on the other
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* core-siblings, if the first logical CPU in a socket passed the sync test.
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* But as the TSC is per-logical CPU and can potentially be modified wrongly
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* by the bios, TSC sync test for smaller duration should be able
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* to catch such errors. Also this will catch the condition where all the
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* cores in the socket doesn't get reset at the same time.
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*/
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static inline unsigned int loop_timeout(int cpu)
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{
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return (cpumask_weight(topology_core_cpumask(cpu)) > 1) ? 2 : 20;
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}
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/*
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* Source CPU calls into this - it waits for the freshly booted
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* target CPU to arrive and then starts the measurement:
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*/
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void check_tsc_sync_source(int cpu)
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{
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int cpus = 2;
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/*
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* No need to check if we already know that the TSC is not
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* synchronized or if we have no TSC.
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*/
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if (unsynchronized_tsc())
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return;
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/*
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* Set the maximum number of test runs to
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* 1 if the CPU does not provide the TSC_ADJUST MSR
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* 3 if the MSR is available, so the target can try to adjust
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*/
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if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
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atomic_set(&test_runs, 1);
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else
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atomic_set(&test_runs, 3);
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retry:
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/*
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* Wait for the target to start or to skip the test:
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*/
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while (atomic_read(&start_count) != cpus - 1) {
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if (atomic_read(&skip_test) > 0) {
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atomic_set(&skip_test, 0);
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return;
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}
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cpu_relax();
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}
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/*
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* Trigger the target to continue into the measurement too:
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*/
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atomic_inc(&start_count);
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check_tsc_warp(loop_timeout(cpu));
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while (atomic_read(&stop_count) != cpus-1)
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cpu_relax();
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/*
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* If the test was successful set the number of runs to zero and
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* stop. If not, decrement the number of runs an check if we can
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* retry. In case of random warps no retry is attempted.
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*/
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if (!nr_warps) {
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atomic_set(&test_runs, 0);
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pr_debug("TSC synchronization [CPU#%d -> CPU#%d]: passed\n",
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smp_processor_id(), cpu);
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} else if (atomic_dec_and_test(&test_runs) || random_warps) {
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/* Force it to 0 if random warps brought us here */
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atomic_set(&test_runs, 0);
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pr_warning("TSC synchronization [CPU#%d -> CPU#%d]:\n",
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smp_processor_id(), cpu);
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pr_warning("Measured %Ld cycles TSC warp between CPUs, "
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"turning off TSC clock.\n", max_warp);
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if (random_warps)
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pr_warning("TSC warped randomly between CPUs\n");
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mark_tsc_unstable("check_tsc_sync_source failed");
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}
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/*
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* Reset it - just in case we boot another CPU later:
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*/
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atomic_set(&start_count, 0);
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random_warps = 0;
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nr_warps = 0;
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max_warp = 0;
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last_tsc = 0;
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/*
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* Let the target continue with the bootup:
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*/
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atomic_inc(&stop_count);
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/*
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* Retry, if there is a chance to do so.
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*/
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if (atomic_read(&test_runs) > 0)
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goto retry;
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}
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/*
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* Freshly booted CPUs call into this:
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*/
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void check_tsc_sync_target(void)
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{
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struct tsc_adjust *cur = this_cpu_ptr(&tsc_adjust);
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unsigned int cpu = smp_processor_id();
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cycles_t cur_max_warp, gbl_max_warp;
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int cpus = 2;
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/* Also aborts if there is no TSC. */
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if (unsynchronized_tsc())
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return;
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/*
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* Store, verify and sanitize the TSC adjust register. If
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* successful skip the test.
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*
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* The test is also skipped when the TSC is marked reliable. This
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* is true for SoCs which have no fallback clocksource. On these
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* SoCs the TSC is frequency synchronized, but still the TSC ADJUST
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* register might have been wreckaged by the BIOS..
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*/
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if (tsc_store_and_check_tsc_adjust(false) || tsc_clocksource_reliable) {
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atomic_inc(&skip_test);
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return;
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}
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retry:
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/*
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* Register this CPU's participation and wait for the
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* source CPU to start the measurement:
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*/
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atomic_inc(&start_count);
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while (atomic_read(&start_count) != cpus)
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cpu_relax();
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cur_max_warp = check_tsc_warp(loop_timeout(cpu));
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/*
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* Store the maximum observed warp value for a potential retry:
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*/
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gbl_max_warp = max_warp;
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/*
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* Ok, we are done:
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*/
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atomic_inc(&stop_count);
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/*
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* Wait for the source CPU to print stuff:
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*/
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while (atomic_read(&stop_count) != cpus)
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cpu_relax();
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/*
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* Reset it for the next sync test:
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*/
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atomic_set(&stop_count, 0);
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/*
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* Check the number of remaining test runs. If not zero, the test
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* failed and a retry with adjusted TSC is possible. If zero the
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* test was either successful or failed terminally.
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*/
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if (!atomic_read(&test_runs))
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return;
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/*
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* If the warp value of this CPU is 0, then the other CPU
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* observed time going backwards so this TSC was ahead and
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* needs to move backwards.
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*/
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if (!cur_max_warp)
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cur_max_warp = -gbl_max_warp;
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/*
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* Add the result to the previous adjustment value.
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*
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* The adjustement value is slightly off by the overhead of the
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* sync mechanism (observed values are ~200 TSC cycles), but this
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* really depends on CPU, node distance and frequency. So
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* compensating for this is hard to get right. Experiments show
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* that the warp is not longer detectable when the observed warp
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* value is used. In the worst case the adjustment needs to go
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* through a 3rd run for fine tuning.
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*/
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cur->adjusted += cur_max_warp;
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pr_warn("TSC ADJUST compensate: CPU%u observed %lld warp. Adjust: %lld\n",
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cpu, cur_max_warp, cur->adjusted);
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wrmsrl(MSR_IA32_TSC_ADJUST, cur->adjusted);
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goto retry;
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}
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#endif /* CONFIG_SMP */
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