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547 lines
14 KiB
C
547 lines
14 KiB
C
/*
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* Sonics Silicon Backplane
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* Broadcom ChipCommon core driver
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*
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* Copyright 2005, Broadcom Corporation
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* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include <linux/ssb/ssb.h>
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#include <linux/ssb/ssb_regs.h>
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#include <linux/pci.h>
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#include "ssb_private.h"
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/* Clock sources */
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enum ssb_clksrc {
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/* PCI clock */
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SSB_CHIPCO_CLKSRC_PCI,
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/* Crystal slow clock oscillator */
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SSB_CHIPCO_CLKSRC_XTALOS,
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/* Low power oscillator */
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SSB_CHIPCO_CLKSRC_LOPWROS,
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};
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static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
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u32 mask, u32 value)
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{
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value &= mask;
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value |= chipco_read32(cc, offset) & ~mask;
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chipco_write32(cc, offset, value);
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return value;
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}
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void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
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enum ssb_clkmode mode)
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{
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struct ssb_device *ccdev = cc->dev;
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struct ssb_bus *bus;
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u32 tmp;
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if (!ccdev)
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return;
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bus = ccdev->bus;
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/* We support SLOW only on 6..9 */
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if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
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mode = SSB_CLKMODE_DYNAMIC;
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if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
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return; /* PMU controls clockmode, separated function needed */
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SSB_WARN_ON(ccdev->id.revision >= 20);
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/* chipcommon cores prior to rev6 don't support dynamic clock control */
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if (ccdev->id.revision < 6)
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return;
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/* ChipCommon cores rev10+ need testing */
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if (ccdev->id.revision >= 10)
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return;
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if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
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return;
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switch (mode) {
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case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
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tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
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tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
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chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
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break;
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case SSB_CLKMODE_FAST:
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if (ccdev->id.revision < 10) {
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ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
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tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
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tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
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tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
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chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
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} else {
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chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
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(chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
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SSB_CHIPCO_SYSCLKCTL_FORCEHT));
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/* udelay(150); TODO: not available in early init */
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}
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break;
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case SSB_CLKMODE_DYNAMIC:
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if (ccdev->id.revision < 10) {
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tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
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tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
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tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
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tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
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if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
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SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
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tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
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chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
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/* For dynamic control, we have to release our xtal_pu
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* "force on" */
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if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
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ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
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} else {
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chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
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(chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
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~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
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}
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break;
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default:
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SSB_WARN_ON(1);
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}
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}
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/* Get the Slow Clock Source */
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static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc)
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{
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struct ssb_bus *bus = cc->dev->bus;
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u32 uninitialized_var(tmp);
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if (cc->dev->id.revision < 6) {
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if (bus->bustype == SSB_BUSTYPE_SSB ||
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bus->bustype == SSB_BUSTYPE_PCMCIA)
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return SSB_CHIPCO_CLKSRC_XTALOS;
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if (bus->bustype == SSB_BUSTYPE_PCI) {
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pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp);
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if (tmp & 0x10)
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return SSB_CHIPCO_CLKSRC_PCI;
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return SSB_CHIPCO_CLKSRC_XTALOS;
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}
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}
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if (cc->dev->id.revision < 10) {
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tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
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tmp &= 0x7;
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if (tmp == 0)
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return SSB_CHIPCO_CLKSRC_LOPWROS;
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if (tmp == 1)
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return SSB_CHIPCO_CLKSRC_XTALOS;
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if (tmp == 2)
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return SSB_CHIPCO_CLKSRC_PCI;
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}
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return SSB_CHIPCO_CLKSRC_XTALOS;
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}
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/* Get maximum or minimum (depending on get_max flag) slowclock frequency. */
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static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max)
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{
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int uninitialized_var(limit);
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enum ssb_clksrc clocksrc;
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int divisor = 1;
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u32 tmp;
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clocksrc = chipco_pctl_get_slowclksrc(cc);
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if (cc->dev->id.revision < 6) {
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switch (clocksrc) {
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case SSB_CHIPCO_CLKSRC_PCI:
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divisor = 64;
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break;
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case SSB_CHIPCO_CLKSRC_XTALOS:
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divisor = 32;
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break;
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default:
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SSB_WARN_ON(1);
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}
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} else if (cc->dev->id.revision < 10) {
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switch (clocksrc) {
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case SSB_CHIPCO_CLKSRC_LOPWROS:
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break;
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case SSB_CHIPCO_CLKSRC_XTALOS:
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case SSB_CHIPCO_CLKSRC_PCI:
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tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
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divisor = (tmp >> 16) + 1;
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divisor *= 4;
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break;
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}
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} else {
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tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL);
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divisor = (tmp >> 16) + 1;
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divisor *= 4;
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}
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switch (clocksrc) {
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case SSB_CHIPCO_CLKSRC_LOPWROS:
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if (get_max)
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limit = 43000;
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else
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limit = 25000;
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break;
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case SSB_CHIPCO_CLKSRC_XTALOS:
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if (get_max)
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limit = 20200000;
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else
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limit = 19800000;
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break;
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case SSB_CHIPCO_CLKSRC_PCI:
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if (get_max)
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limit = 34000000;
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else
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limit = 25000000;
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break;
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}
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limit /= divisor;
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return limit;
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}
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static void chipco_powercontrol_init(struct ssb_chipcommon *cc)
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{
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struct ssb_bus *bus = cc->dev->bus;
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if (bus->chip_id == 0x4321) {
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if (bus->chip_rev == 0)
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chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4);
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else if (bus->chip_rev == 1)
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chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4);
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}
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if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
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return;
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if (cc->dev->id.revision >= 10) {
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/* Set Idle Power clock rate to 1Mhz */
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chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
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(chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
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0x0000FFFF) | 0x00040000);
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} else {
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int maxfreq;
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maxfreq = chipco_pctl_clockfreqlimit(cc, 1);
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chipco_write32(cc, SSB_CHIPCO_PLLONDELAY,
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(maxfreq * 150 + 999999) / 1000000);
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chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY,
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(maxfreq * 15 + 999999) / 1000000);
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}
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}
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/* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */
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static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc)
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{
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struct ssb_bus *bus = cc->dev->bus;
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switch (bus->chip_id) {
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case 0x4312:
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case 0x4322:
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case 0x4328:
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return 7000;
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case 0x4325:
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/* TODO: */
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default:
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return 15000;
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}
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}
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/* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */
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static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
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{
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struct ssb_bus *bus = cc->dev->bus;
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int minfreq;
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unsigned int tmp;
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u32 pll_on_delay;
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if (bus->bustype != SSB_BUSTYPE_PCI)
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return;
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if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
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cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc);
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return;
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}
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if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
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return;
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minfreq = chipco_pctl_clockfreqlimit(cc, 0);
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pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY);
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tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq;
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SSB_WARN_ON(tmp & ~0xFFFF);
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cc->fast_pwrup_delay = tmp;
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}
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void ssb_chipcommon_init(struct ssb_chipcommon *cc)
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{
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if (!cc->dev)
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return; /* We don't have a ChipCommon */
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if (cc->dev->id.revision >= 11)
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cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
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ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
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if (cc->dev->id.revision >= 20) {
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chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
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chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
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}
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ssb_pmu_init(cc);
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chipco_powercontrol_init(cc);
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ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
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calc_fast_powerup_delay(cc);
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}
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void ssb_chipco_suspend(struct ssb_chipcommon *cc)
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{
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if (!cc->dev)
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return;
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ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
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}
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void ssb_chipco_resume(struct ssb_chipcommon *cc)
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{
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if (!cc->dev)
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return;
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chipco_powercontrol_init(cc);
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ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
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}
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/* Get the processor clock */
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void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
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u32 *plltype, u32 *n, u32 *m)
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{
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*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
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*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
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switch (*plltype) {
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case SSB_PLLTYPE_2:
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case SSB_PLLTYPE_4:
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case SSB_PLLTYPE_6:
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case SSB_PLLTYPE_7:
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*m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
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break;
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case SSB_PLLTYPE_3:
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/* 5350 uses m2 to control mips */
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*m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
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break;
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default:
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*m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
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break;
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}
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}
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/* Get the bus clock */
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void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
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u32 *plltype, u32 *n, u32 *m)
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{
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*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
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*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
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switch (*plltype) {
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case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
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*m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
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break;
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case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
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if (cc->dev->bus->chip_id != 0x5365) {
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*m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
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break;
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}
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/* Fallthough */
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default:
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*m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
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}
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}
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void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
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unsigned long ns)
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{
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struct ssb_device *dev = cc->dev;
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struct ssb_bus *bus = dev->bus;
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u32 tmp;
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/* set register for external IO to control LED. */
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chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11);
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tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */
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tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 40ns */
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tmp |= DIV_ROUND_UP(240, ns); /* Waitcount-0 = 240ns */
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chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
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/* Set timing for the flash */
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tmp = DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_3_SHIFT; /* Waitcount-3 = 10nS */
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tmp |= DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_1_SHIFT; /* Waitcount-1 = 10nS */
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tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120nS */
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if ((bus->chip_id == 0x5365) ||
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(dev->id.revision < 9))
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chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp);
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if ((bus->chip_id == 0x5365) ||
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(dev->id.revision < 9) ||
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((bus->chip_id == 0x5350) && (bus->chip_rev == 0)))
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chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp);
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if (bus->chip_id == 0x5350) {
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/* Enable EXTIF */
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tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */
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tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT; /* Waitcount-2 = 20ns */
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tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */
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tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120ns */
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chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
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}
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}
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/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
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void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
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{
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/* instant NMI */
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chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
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}
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void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
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{
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chipco_write32_masked(cc, SSB_CHIPCO_IRQMASK, mask, value);
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}
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u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask)
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{
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return chipco_read32(cc, SSB_CHIPCO_IRQSTAT) & mask;
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}
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u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask)
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{
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return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
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}
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u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
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{
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return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
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}
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u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
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{
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return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
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}
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u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
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{
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return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
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}
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EXPORT_SYMBOL(ssb_chipco_gpio_control);
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u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
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{
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return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
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}
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u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
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{
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return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
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}
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#ifdef CONFIG_SSB_SERIAL
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int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
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struct ssb_serial_port *ports)
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{
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struct ssb_bus *bus = cc->dev->bus;
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int nr_ports = 0;
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u32 plltype;
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unsigned int irq;
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u32 baud_base, div;
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u32 i, n;
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unsigned int ccrev = cc->dev->id.revision;
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plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
|
|
irq = ssb_mips_irq(cc->dev);
|
|
|
|
if (plltype == SSB_PLLTYPE_1) {
|
|
/* PLL clock */
|
|
baud_base = ssb_calc_clock_rate(plltype,
|
|
chipco_read32(cc, SSB_CHIPCO_CLOCK_N),
|
|
chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
|
|
div = 1;
|
|
} else {
|
|
if (ccrev == 20) {
|
|
/* BCM5354 uses constant 25MHz clock */
|
|
baud_base = 25000000;
|
|
div = 48;
|
|
/* Set the override bit so we don't divide it */
|
|
chipco_write32(cc, SSB_CHIPCO_CORECTL,
|
|
chipco_read32(cc, SSB_CHIPCO_CORECTL)
|
|
| SSB_CHIPCO_CORECTL_UARTCLK0);
|
|
} else if ((ccrev >= 11) && (ccrev != 15)) {
|
|
/* Fixed ALP clock */
|
|
baud_base = 20000000;
|
|
if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
|
|
/* FIXME: baud_base is different for devices with a PMU */
|
|
SSB_WARN_ON(1);
|
|
}
|
|
div = 1;
|
|
if (ccrev >= 21) {
|
|
/* Turn off UART clock before switching clocksource. */
|
|
chipco_write32(cc, SSB_CHIPCO_CORECTL,
|
|
chipco_read32(cc, SSB_CHIPCO_CORECTL)
|
|
& ~SSB_CHIPCO_CORECTL_UARTCLKEN);
|
|
}
|
|
/* Set the override bit so we don't divide it */
|
|
chipco_write32(cc, SSB_CHIPCO_CORECTL,
|
|
chipco_read32(cc, SSB_CHIPCO_CORECTL)
|
|
| SSB_CHIPCO_CORECTL_UARTCLK0);
|
|
if (ccrev >= 21) {
|
|
/* Re-enable the UART clock. */
|
|
chipco_write32(cc, SSB_CHIPCO_CORECTL,
|
|
chipco_read32(cc, SSB_CHIPCO_CORECTL)
|
|
| SSB_CHIPCO_CORECTL_UARTCLKEN);
|
|
}
|
|
} else if (ccrev >= 3) {
|
|
/* Internal backplane clock */
|
|
baud_base = ssb_clockspeed(bus);
|
|
div = chipco_read32(cc, SSB_CHIPCO_CLKDIV)
|
|
& SSB_CHIPCO_CLKDIV_UART;
|
|
} else {
|
|
/* Fixed internal backplane clock */
|
|
baud_base = 88000000;
|
|
div = 48;
|
|
}
|
|
|
|
/* Clock source depends on strapping if UartClkOverride is unset */
|
|
if ((ccrev > 0) &&
|
|
!(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
|
|
if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
|
|
SSB_CHIPCO_CAP_UARTCLK_INT) {
|
|
/* Internal divided backplane clock */
|
|
baud_base /= div;
|
|
} else {
|
|
/* Assume external clock of 1.8432 MHz */
|
|
baud_base = 1843200;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Determine the registers of the UARTs */
|
|
n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART);
|
|
for (i = 0; i < n; i++) {
|
|
void __iomem *cc_mmio;
|
|
void __iomem *uart_regs;
|
|
|
|
cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
|
|
uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
|
|
/* Offset changed at after rev 0 */
|
|
if (ccrev == 0)
|
|
uart_regs += (i * 8);
|
|
else
|
|
uart_regs += (i * 256);
|
|
|
|
nr_ports++;
|
|
ports[i].regs = uart_regs;
|
|
ports[i].irq = irq;
|
|
ports[i].baud_base = baud_base;
|
|
ports[i].reg_shift = 0;
|
|
}
|
|
|
|
return nr_ports;
|
|
}
|
|
#endif /* CONFIG_SSB_SERIAL */
|