linux/drivers/gpu
Alex Deucher d474ea7e52 drm/radeon: fix VM flush on SI (v3)
We need to wait for the GPUVM flush to complete.  There
was some confusion as to how this mechanism was supposed
to work.  The operation is not atomic.  For GPU initiated
invalidations you need to read back a VM register to
introduce enough latency for the update to complete.

v2: drop gart changes
v3: just read back rather than polling

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2015-01-08 09:36:50 -05:00
..
drm drm/radeon: fix VM flush on SI (v3) 2015-01-08 09:36:50 -05:00
host1x gpu: host1x: mipi: Set MIPI_CAL_BIAS_PAD_CFG1 register 2014-11-13 16:11:57 +01:00
ipu-v3 [media] gpu: ipu-v3: Make use of media_bus_format enum 2014-11-14 17:55:27 -02:00
vga Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 2014-10-13 16:23:15 +02:00
Makefile gpu: ipu-v3: Move i.MX IPUv3 core driver out of staging 2014-06-04 11:06:52 +02:00