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1bf4b15b19
We are missing alwon ethernet clock for dm814x and this prevents us
from probing the CPSW with device tree only data. Looks like Ethernet
currently only works if it has been enabled in the bootloader.
Looks like relying on the bootloader clocks is not an issue with the
mainline kernel currently, but it will be an issue when configuring
CPSW Ethernet to probe with device tree data only as we will be managing
the clocks.
Fixes: 26ca2e9738 ("clk: ti: dm814: add clkctrl clock data")
Cc: linux-clk@vger.kernel.org
Cc: Graeme Smecher <gsmecher@threespeedlogic.com>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
119 lines
3.4 KiB
C
119 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/ti.h>
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#include <linux/of_platform.h>
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#include <dt-bindings/clock/dm814.h>
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#include "clock.h"
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static const struct omap_clkctrl_reg_data dm814_default_clkctrl_regs[] __initconst = {
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{ DM814_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "pll260dcoclkldo" },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data dm814_alwon_clkctrl_regs[] __initconst = {
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{ DM814_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
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{ DM814_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
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{ DM814_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
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{ DM814_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
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{ DM814_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
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{ DM814_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
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{ DM814_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
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{ DM814_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
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{ DM814_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
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{ DM814_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
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{ DM814_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "mpu_ck" },
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{ DM814_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
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{ DM814_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
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{ DM814_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
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{ DM814_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
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{ DM814_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
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{ DM814_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
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{ DM814_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
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{ DM814_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
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{ DM814_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
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{ 0 },
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};
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static const struct
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omap_clkctrl_reg_data dm814_alwon_ethernet_clkctrl_regs[] __initconst = {
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{ 0, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
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};
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const struct omap_clkctrl_data dm814_clkctrl_data[] __initconst = {
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{ 0x48180500, dm814_default_clkctrl_regs },
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{ 0x48181400, dm814_alwon_clkctrl_regs },
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{ 0x481815d4, dm814_alwon_ethernet_clkctrl_regs },
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{ 0 },
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};
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static struct ti_dt_clk dm814_clks[] = {
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DT_CLK(NULL, "timer_sys_ck", "devosc_ck"),
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{ .node_name = NULL },
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};
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static bool timer_clocks_initialized;
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static int __init dm814x_adpll_early_init(void)
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{
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struct device_node *np;
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if (!timer_clocks_initialized)
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return -ENODEV;
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np = of_find_node_by_name(NULL, "pllss");
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if (!np) {
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pr_err("Could not find node for plls\n");
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return -ENODEV;
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}
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of_platform_populate(np, NULL, NULL, NULL);
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of_node_put(np);
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return 0;
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}
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core_initcall(dm814x_adpll_early_init);
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static const char * const init_clocks[] = {
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"pll040clkout", /* MPU 481c5040.adpll.clkout */
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"pll290clkout", /* DDR 481c5290.adpll.clkout */
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};
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static int __init dm814x_adpll_enable_init_clocks(void)
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{
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int i, err;
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if (!timer_clocks_initialized)
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return -ENODEV;
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for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
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struct clk *clock;
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clock = clk_get(NULL, init_clocks[i]);
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if (WARN(IS_ERR(clock), "could not find init clock %s\n",
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init_clocks[i]))
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continue;
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err = clk_prepare_enable(clock);
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if (WARN(err, "could not enable init clock %s\n",
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init_clocks[i]))
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continue;
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}
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return 0;
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}
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postcore_initcall(dm814x_adpll_enable_init_clocks);
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int __init dm814x_dt_clk_init(void)
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{
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ti_dt_clocks_register(dm814_clks);
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omap2_clk_disable_autoidle_all();
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ti_clk_add_aliases();
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omap2_clk_enable_init_clocks(NULL, 0);
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timer_clocks_initialized = true;
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return 0;
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}
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