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d4647f0a2a
The Spectre-v2 mitigation code is pretty unwieldy and hard to maintain. This is largely due to it being written hastily, without much clue as to how things would pan out, and also because it ends up mixing policy and state in such a way that it is very difficult to figure out what's going on. Rewrite the Spectre-v2 mitigation so that it clearly separates state from policy and follows a more structured approach to handling the mitigation. Signed-off-by: Will Deacon <will@kernel.org>
750 lines
19 KiB
C
750 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Contains CPU specific errata definitions
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*
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* Copyright (C) 2014 ARM Ltd.
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*/
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#include <linux/arm-smccc.h>
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#include <linux/types.h>
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#include <linux/cpu.h>
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#include <asm/cpu.h>
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#include <asm/cputype.h>
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#include <asm/cpufeature.h>
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#include <asm/kvm_asm.h>
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#include <asm/smp_plat.h>
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static bool __maybe_unused
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is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
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{
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const struct arm64_midr_revidr *fix;
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u32 midr = read_cpuid_id(), revidr;
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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if (!is_midr_in_range(midr, &entry->midr_range))
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return false;
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midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
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revidr = read_cpuid(REVIDR_EL1);
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for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
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if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
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return false;
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return true;
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}
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static bool __maybe_unused
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is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
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}
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static bool __maybe_unused
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is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
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{
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u32 model;
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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model = read_cpuid_id();
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model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
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MIDR_ARCHITECTURE_MASK;
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return model == entry->midr_range.model;
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}
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static bool
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has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
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u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask;
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u64 ctr_raw, ctr_real;
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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/*
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* We want to make sure that all the CPUs in the system expose
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* a consistent CTR_EL0 to make sure that applications behaves
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* correctly with migration.
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*
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* If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 :
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*
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* 1) It is safe if the system doesn't support IDC, as CPU anyway
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* reports IDC = 0, consistent with the rest.
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*
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* 2) If the system has IDC, it is still safe as we trap CTR_EL0
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* access on this CPU via the ARM64_HAS_CACHE_IDC capability.
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*
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* So, we need to make sure either the raw CTR_EL0 or the effective
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* CTR_EL0 matches the system's copy to allow a secondary CPU to boot.
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*/
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ctr_raw = read_cpuid_cachetype() & mask;
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ctr_real = read_cpuid_effective_cachetype() & mask;
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return (ctr_real != sys) && (ctr_raw != sys);
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}
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static void
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cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap)
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{
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u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
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bool enable_uct_trap = false;
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/* Trap CTR_EL0 access on this CPU, only if it has a mismatch */
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if ((read_cpuid_cachetype() & mask) !=
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(arm64_ftr_reg_ctrel0.sys_val & mask))
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enable_uct_trap = true;
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/* ... or if the system is affected by an erratum */
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if (cap->capability == ARM64_WORKAROUND_1542419)
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enable_uct_trap = true;
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if (enable_uct_trap)
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sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
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}
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DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required);
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int ssbd_state __read_mostly = ARM64_SSBD_KERNEL;
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static bool __ssb_safe = true;
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static const struct ssbd_options {
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const char *str;
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int state;
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} ssbd_options[] = {
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{ "force-on", ARM64_SSBD_FORCE_ENABLE, },
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{ "force-off", ARM64_SSBD_FORCE_DISABLE, },
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{ "kernel", ARM64_SSBD_KERNEL, },
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};
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static int __init ssbd_cfg(char *buf)
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{
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int i;
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if (!buf || !buf[0])
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return -EINVAL;
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for (i = 0; i < ARRAY_SIZE(ssbd_options); i++) {
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int len = strlen(ssbd_options[i].str);
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if (strncmp(buf, ssbd_options[i].str, len))
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continue;
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ssbd_state = ssbd_options[i].state;
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return 0;
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}
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return -EINVAL;
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}
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early_param("ssbd", ssbd_cfg);
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void __init arm64_update_smccc_conduit(struct alt_instr *alt,
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__le32 *origptr, __le32 *updptr,
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int nr_inst)
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{
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u32 insn;
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BUG_ON(nr_inst != 1);
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switch (arm_smccc_1_1_get_conduit()) {
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case SMCCC_CONDUIT_HVC:
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insn = aarch64_insn_get_hvc_value();
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break;
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case SMCCC_CONDUIT_SMC:
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insn = aarch64_insn_get_smc_value();
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break;
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default:
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return;
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}
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*updptr = cpu_to_le32(insn);
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}
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void __init arm64_enable_wa2_handling(struct alt_instr *alt,
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__le32 *origptr, __le32 *updptr,
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int nr_inst)
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{
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BUG_ON(nr_inst != 1);
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/*
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* Only allow mitigation on EL1 entry/exit and guest
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* ARCH_WORKAROUND_2 handling if the SSBD state allows it to
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* be flipped.
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*/
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if (arm64_get_ssbd_state() == ARM64_SSBD_KERNEL)
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*updptr = cpu_to_le32(aarch64_insn_gen_nop());
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}
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void arm64_set_ssbd_mitigation(bool state)
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{
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int conduit;
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if (this_cpu_has_cap(ARM64_SSBS)) {
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if (state)
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asm volatile(SET_PSTATE_SSBS(0));
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else
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asm volatile(SET_PSTATE_SSBS(1));
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return;
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}
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conduit = arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_WORKAROUND_2, state,
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NULL);
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WARN_ON_ONCE(conduit == SMCCC_CONDUIT_NONE);
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}
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static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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struct arm_smccc_res res;
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bool required = true;
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s32 val;
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bool this_cpu_safe = false;
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int conduit;
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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if (cpu_mitigations_off())
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ssbd_state = ARM64_SSBD_FORCE_DISABLE;
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/* delay setting __ssb_safe until we get a firmware response */
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if (is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list))
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this_cpu_safe = true;
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if (this_cpu_has_cap(ARM64_SSBS)) {
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if (!this_cpu_safe)
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__ssb_safe = false;
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required = false;
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goto out_printmsg;
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}
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conduit = arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
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ARM_SMCCC_ARCH_WORKAROUND_2, &res);
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if (conduit == SMCCC_CONDUIT_NONE) {
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ssbd_state = ARM64_SSBD_UNKNOWN;
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if (!this_cpu_safe)
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__ssb_safe = false;
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return false;
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}
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val = (s32)res.a0;
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switch (val) {
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case SMCCC_RET_NOT_SUPPORTED:
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ssbd_state = ARM64_SSBD_UNKNOWN;
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if (!this_cpu_safe)
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__ssb_safe = false;
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return false;
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/* machines with mixed mitigation requirements must not return this */
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case SMCCC_RET_NOT_REQUIRED:
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pr_info_once("%s mitigation not required\n", entry->desc);
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ssbd_state = ARM64_SSBD_MITIGATED;
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return false;
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case SMCCC_RET_SUCCESS:
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__ssb_safe = false;
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required = true;
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break;
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case 1: /* Mitigation not required on this CPU */
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required = false;
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break;
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default:
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WARN_ON(1);
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if (!this_cpu_safe)
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__ssb_safe = false;
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return false;
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}
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switch (ssbd_state) {
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case ARM64_SSBD_FORCE_DISABLE:
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arm64_set_ssbd_mitigation(false);
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required = false;
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break;
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case ARM64_SSBD_KERNEL:
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if (required) {
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__this_cpu_write(arm64_ssbd_callback_required, 1);
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arm64_set_ssbd_mitigation(true);
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}
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break;
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case ARM64_SSBD_FORCE_ENABLE:
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arm64_set_ssbd_mitigation(true);
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required = true;
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break;
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default:
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WARN_ON(1);
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break;
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}
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out_printmsg:
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switch (ssbd_state) {
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case ARM64_SSBD_FORCE_DISABLE:
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pr_info_once("%s disabled from command-line\n", entry->desc);
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break;
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case ARM64_SSBD_FORCE_ENABLE:
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pr_info_once("%s forced from command-line\n", entry->desc);
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break;
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}
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return required;
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}
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static void cpu_enable_ssbd_mitigation(const struct arm64_cpu_capabilities *cap)
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{
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if (ssbd_state != ARM64_SSBD_FORCE_DISABLE)
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cap->matches(cap, SCOPE_LOCAL_CPU);
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}
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/* known invulnerable cores */
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static const struct midr_range arm64_ssb_cpus[] = {
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
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MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
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MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
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MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
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{},
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};
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#ifdef CONFIG_ARM64_ERRATUM_1463225
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DEFINE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
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static bool
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has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode();
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}
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#endif
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static void __maybe_unused
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cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
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{
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sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);
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}
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#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
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.matches = is_affected_midr_range, \
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.midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
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#define CAP_MIDR_ALL_VERSIONS(model) \
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.matches = is_affected_midr_range, \
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.midr_range = MIDR_ALL_VERSIONS(model)
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#define MIDR_FIXED(rev, revidr_mask) \
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.fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
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#define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
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CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
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#define CAP_MIDR_RANGE_LIST(list) \
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.matches = is_affected_midr_range_list, \
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.midr_range_list = list
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/* Errata affecting a range of revisions of given model variant */
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#define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \
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ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
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/* Errata affecting a single variant/revision of a model */
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#define ERRATA_MIDR_REV(model, var, rev) \
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ERRATA_MIDR_RANGE(model, var, rev, var, rev)
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/* Errata affecting all variants/revisions of a given a model */
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#define ERRATA_MIDR_ALL_VERSIONS(model) \
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
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CAP_MIDR_ALL_VERSIONS(model)
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/* Errata affecting a list of midr ranges, with same work around */
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#define ERRATA_MIDR_RANGE_LIST(midr_list) \
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
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CAP_MIDR_RANGE_LIST(midr_list)
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static const __maybe_unused struct midr_range tx2_family_cpus[] = {
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MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
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MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
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{},
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};
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static bool __maybe_unused
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needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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int i;
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if (!is_affected_midr_range_list(entry, scope) ||
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!is_hyp_mode_available())
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return false;
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for_each_possible_cpu(i) {
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if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0)
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return true;
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}
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return false;
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}
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static bool __maybe_unused
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has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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u32 midr = read_cpuid_id();
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bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT);
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const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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return is_midr_in_range(midr, &range) && has_dic;
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}
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#ifdef CONFIG_RANDOMIZE_BASE
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static const struct midr_range ca57_a72[] = {
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
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{},
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};
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#endif
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#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
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static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
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#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
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{
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ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0)
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},
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{
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.midr_range.model = MIDR_QCOM_KRYO,
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.matches = is_kryo_midr,
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_1286807
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{
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ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
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},
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#endif
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{},
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};
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#endif
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#ifdef CONFIG_CAVIUM_ERRATUM_27456
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const struct midr_range cavium_erratum_27456_cpus[] = {
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/* Cavium ThunderX, T88 pass 1.x - 2.1 */
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MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1),
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/* Cavium ThunderX, T81 pass 1.0 */
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MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
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{},
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};
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#endif
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#ifdef CONFIG_CAVIUM_ERRATUM_30115
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static const struct midr_range cavium_erratum_30115_cpus[] = {
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/* Cavium ThunderX, T88 pass 1.x - 2.2 */
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MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2),
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/* Cavium ThunderX, T81 pass 1.0 - 1.2 */
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MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
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/* Cavium ThunderX, T83 pass 1.0 */
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MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
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{},
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};
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#endif
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#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
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static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {
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{
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ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
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},
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{
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.midr_range.model = MIDR_QCOM_KRYO,
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.matches = is_kryo_midr,
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},
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{},
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};
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#endif
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#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
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static const struct midr_range workaround_clean_cache[] = {
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#if defined(CONFIG_ARM64_ERRATUM_826319) || \
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defined(CONFIG_ARM64_ERRATUM_827319) || \
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defined(CONFIG_ARM64_ERRATUM_824069)
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/* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */
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MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_819472
|
|
/* Cortex-A53 r0p[01] : ARM errata 819472 */
|
|
MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
|
|
#endif
|
|
{},
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARM64_ERRATUM_1418040
|
|
/*
|
|
* - 1188873 affects r0p0 to r2p0
|
|
* - 1418040 affects r0p0 to r3p1
|
|
*/
|
|
static const struct midr_range erratum_1418040_list[] = {
|
|
/* Cortex-A76 r0p0 to r3p1 */
|
|
MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
|
|
/* Neoverse-N1 r0p0 to r3p1 */
|
|
MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),
|
|
/* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
|
|
MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
|
|
{},
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARM64_ERRATUM_845719
|
|
static const struct midr_range erratum_845719_list[] = {
|
|
/* Cortex-A53 r0p[01234] */
|
|
MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
|
|
/* Brahma-B53 r0p[0] */
|
|
MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
|
|
{},
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARM64_ERRATUM_843419
|
|
static const struct arm64_cpu_capabilities erratum_843419_list[] = {
|
|
{
|
|
/* Cortex-A53 r0p[01234] */
|
|
.matches = is_affected_midr_range,
|
|
ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
|
|
MIDR_FIXED(0x4, BIT(8)),
|
|
},
|
|
{
|
|
/* Brahma-B53 r0p[0] */
|
|
.matches = is_affected_midr_range,
|
|
ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
|
|
},
|
|
{},
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
|
|
static const struct midr_range erratum_speculative_at_list[] = {
|
|
#ifdef CONFIG_ARM64_ERRATUM_1165522
|
|
/* Cortex A76 r0p0 to r2p0 */
|
|
MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_1319367
|
|
MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
|
|
MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_1530923
|
|
/* Cortex A55 r0p0 to r2p0 */
|
|
MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),
|
|
/* Kryo4xx Silver (rdpe => r1p0) */
|
|
MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
|
|
#endif
|
|
{},
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARM64_ERRATUM_1463225
|
|
static const struct midr_range erratum_1463225[] = {
|
|
/* Cortex-A76 r0p0 - r3p1 */
|
|
MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
|
|
/* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
|
|
MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
|
|
{},
|
|
};
|
|
#endif
|
|
|
|
const struct arm64_cpu_capabilities arm64_errata[] = {
|
|
#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
|
|
{
|
|
.desc = "ARM errata 826319, 827319, 824069, or 819472",
|
|
.capability = ARM64_WORKAROUND_CLEAN_CACHE,
|
|
ERRATA_MIDR_RANGE_LIST(workaround_clean_cache),
|
|
.cpu_enable = cpu_enable_cache_maint_trap,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_832075
|
|
{
|
|
/* Cortex-A57 r0p0 - r1p2 */
|
|
.desc = "ARM erratum 832075",
|
|
.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
|
|
ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
|
|
0, 0,
|
|
1, 2),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_834220
|
|
{
|
|
/* Cortex-A57 r0p0 - r1p2 */
|
|
.desc = "ARM erratum 834220",
|
|
.capability = ARM64_WORKAROUND_834220,
|
|
ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
|
|
0, 0,
|
|
1, 2),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_843419
|
|
{
|
|
.desc = "ARM erratum 843419",
|
|
.capability = ARM64_WORKAROUND_843419,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.matches = cpucap_multi_entry_cap_matches,
|
|
.match_list = erratum_843419_list,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_845719
|
|
{
|
|
.desc = "ARM erratum 845719",
|
|
.capability = ARM64_WORKAROUND_845719,
|
|
ERRATA_MIDR_RANGE_LIST(erratum_845719_list),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CAVIUM_ERRATUM_23154
|
|
{
|
|
/* Cavium ThunderX, pass 1.x */
|
|
.desc = "Cavium erratum 23154",
|
|
.capability = ARM64_WORKAROUND_CAVIUM_23154,
|
|
ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CAVIUM_ERRATUM_27456
|
|
{
|
|
.desc = "Cavium erratum 27456",
|
|
.capability = ARM64_WORKAROUND_CAVIUM_27456,
|
|
ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CAVIUM_ERRATUM_30115
|
|
{
|
|
.desc = "Cavium erratum 30115",
|
|
.capability = ARM64_WORKAROUND_CAVIUM_30115,
|
|
ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus),
|
|
},
|
|
#endif
|
|
{
|
|
.desc = "Mismatched cache type (CTR_EL0)",
|
|
.capability = ARM64_MISMATCHED_CACHE_TYPE,
|
|
.matches = has_mismatched_cache_type,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.cpu_enable = cpu_enable_trap_ctr_access,
|
|
},
|
|
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
|
|
{
|
|
.desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
|
|
.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.matches = cpucap_multi_entry_cap_matches,
|
|
.match_list = qcom_erratum_1003_list,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
|
|
{
|
|
.desc = "Qualcomm erratum 1009, or ARM erratum 1286807",
|
|
.capability = ARM64_WORKAROUND_REPEAT_TLBI,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.matches = cpucap_multi_entry_cap_matches,
|
|
.match_list = arm64_repeat_tlbi_list,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_858921
|
|
{
|
|
/* Cortex-A73 all versions */
|
|
.desc = "ARM erratum 858921",
|
|
.capability = ARM64_WORKAROUND_858921,
|
|
ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
|
|
},
|
|
#endif
|
|
{
|
|
.desc = "Spectre-v2",
|
|
.capability = ARM64_SPECTRE_V2,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.matches = has_spectre_v2,
|
|
.cpu_enable = spectre_v2_enable_mitigation,
|
|
},
|
|
#ifdef CONFIG_RANDOMIZE_BASE
|
|
{
|
|
.desc = "EL2 vector hardening",
|
|
.capability = ARM64_HARDEN_EL2_VECTORS,
|
|
ERRATA_MIDR_RANGE_LIST(ca57_a72),
|
|
},
|
|
#endif
|
|
{
|
|
.desc = "Speculative Store Bypass Disable",
|
|
.capability = ARM64_SSBD,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.matches = has_ssbd_mitigation,
|
|
.cpu_enable = cpu_enable_ssbd_mitigation,
|
|
.midr_range_list = arm64_ssb_cpus,
|
|
},
|
|
#ifdef CONFIG_ARM64_ERRATUM_1418040
|
|
{
|
|
.desc = "ARM erratum 1418040",
|
|
.capability = ARM64_WORKAROUND_1418040,
|
|
ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
|
|
.type = (ARM64_CPUCAP_SCOPE_LOCAL_CPU |
|
|
ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
|
|
{
|
|
.desc = "ARM errata 1165522, 1319367, or 1530923",
|
|
.capability = ARM64_WORKAROUND_SPECULATIVE_AT,
|
|
ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_1463225
|
|
{
|
|
.desc = "ARM erratum 1463225",
|
|
.capability = ARM64_WORKAROUND_1463225,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.matches = has_cortex_a76_erratum_1463225,
|
|
.midr_range_list = erratum_1463225,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CAVIUM_TX2_ERRATUM_219
|
|
{
|
|
.desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)",
|
|
.capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM,
|
|
ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
|
|
.matches = needs_tx2_tvm_workaround,
|
|
},
|
|
{
|
|
.desc = "Cavium ThunderX2 erratum 219 (PRFM removal)",
|
|
.capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM,
|
|
ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_1542419
|
|
{
|
|
/* we depend on the firmware portion for correctness */
|
|
.desc = "ARM erratum 1542419 (kernel portion)",
|
|
.capability = ARM64_WORKAROUND_1542419,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.matches = has_neoverse_n1_erratum_1542419,
|
|
.cpu_enable = cpu_enable_trap_ctr_access,
|
|
},
|
|
#endif
|
|
{
|
|
}
|
|
};
|
|
|
|
ssize_t cpu_show_spec_store_bypass(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
if (__ssb_safe)
|
|
return sprintf(buf, "Not affected\n");
|
|
|
|
switch (ssbd_state) {
|
|
case ARM64_SSBD_KERNEL:
|
|
case ARM64_SSBD_FORCE_ENABLE:
|
|
return sprintf(buf, "Mitigation: Speculative Store Bypass disabled via prctl\n");
|
|
}
|
|
|
|
return sprintf(buf, "Vulnerable\n");
|
|
}
|