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690daddcb6
Add a compatible string for WPCM450, which has essentially the same timer controller. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20210320181610.680870-11-j.neuschaefer@gmx.net
214 lines
5.7 KiB
C
214 lines
5.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2014-2018 Nuvoton Technologies tomer.maimon@nuvoton.com
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* All rights reserved.
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*
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* Copyright 2017 Google, Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/clockchips.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include "timer-of.h"
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/* Timers registers */
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#define NPCM7XX_REG_TCSR0 0x0 /* Timer 0 Control and Status Register */
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#define NPCM7XX_REG_TICR0 0x8 /* Timer 0 Initial Count Register */
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#define NPCM7XX_REG_TCSR1 0x4 /* Timer 1 Control and Status Register */
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#define NPCM7XX_REG_TICR1 0xc /* Timer 1 Initial Count Register */
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#define NPCM7XX_REG_TDR1 0x14 /* Timer 1 Data Register */
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#define NPCM7XX_REG_TISR 0x18 /* Timer Interrupt Status Register */
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/* Timers control */
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#define NPCM7XX_Tx_RESETINT 0x1f
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#define NPCM7XX_Tx_PERIOD BIT(27)
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#define NPCM7XX_Tx_INTEN BIT(29)
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#define NPCM7XX_Tx_COUNTEN BIT(30)
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#define NPCM7XX_Tx_ONESHOT 0x0
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#define NPCM7XX_Tx_OPER GENMASK(28, 27)
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#define NPCM7XX_Tx_MIN_PRESCALE 0x1
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#define NPCM7XX_Tx_TDR_MASK_BITS 24
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#define NPCM7XX_Tx_MAX_CNT 0xFFFFFF
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#define NPCM7XX_T0_CLR_INT 0x1
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#define NPCM7XX_Tx_CLR_CSR 0x0
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/* Timers operating mode */
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#define NPCM7XX_START_PERIODIC_Tx (NPCM7XX_Tx_PERIOD | NPCM7XX_Tx_COUNTEN | \
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NPCM7XX_Tx_INTEN | \
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NPCM7XX_Tx_MIN_PRESCALE)
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#define NPCM7XX_START_ONESHOT_Tx (NPCM7XX_Tx_ONESHOT | NPCM7XX_Tx_COUNTEN | \
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NPCM7XX_Tx_INTEN | \
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NPCM7XX_Tx_MIN_PRESCALE)
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#define NPCM7XX_START_Tx (NPCM7XX_Tx_COUNTEN | NPCM7XX_Tx_PERIOD | \
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NPCM7XX_Tx_MIN_PRESCALE)
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#define NPCM7XX_DEFAULT_CSR (NPCM7XX_Tx_CLR_CSR | NPCM7XX_Tx_MIN_PRESCALE)
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static int npcm7xx_timer_resume(struct clock_event_device *evt)
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{
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struct timer_of *to = to_timer_of(evt);
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u32 val;
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val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
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val |= NPCM7XX_Tx_COUNTEN;
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writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
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return 0;
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}
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static int npcm7xx_timer_shutdown(struct clock_event_device *evt)
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{
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struct timer_of *to = to_timer_of(evt);
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u32 val;
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val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
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val &= ~NPCM7XX_Tx_COUNTEN;
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writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
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return 0;
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}
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static int npcm7xx_timer_oneshot(struct clock_event_device *evt)
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{
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struct timer_of *to = to_timer_of(evt);
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u32 val;
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val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
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val &= ~NPCM7XX_Tx_OPER;
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val |= NPCM7XX_START_ONESHOT_Tx;
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writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
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return 0;
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}
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static int npcm7xx_timer_periodic(struct clock_event_device *evt)
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{
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struct timer_of *to = to_timer_of(evt);
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u32 val;
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writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
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val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
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val &= ~NPCM7XX_Tx_OPER;
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val |= NPCM7XX_START_PERIODIC_Tx;
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writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
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return 0;
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}
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static int npcm7xx_clockevent_set_next_event(unsigned long evt,
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struct clock_event_device *clk)
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{
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struct timer_of *to = to_timer_of(clk);
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u32 val;
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writel(evt, timer_of_base(to) + NPCM7XX_REG_TICR0);
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val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
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val |= NPCM7XX_START_Tx;
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writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
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return 0;
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}
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static irqreturn_t npcm7xx_timer0_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = (struct clock_event_device *)dev_id;
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struct timer_of *to = to_timer_of(evt);
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writel(NPCM7XX_T0_CLR_INT, timer_of_base(to) + NPCM7XX_REG_TISR);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct timer_of npcm7xx_to = {
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.flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
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.clkevt = {
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.name = "npcm7xx-timer0",
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.features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT,
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.set_next_event = npcm7xx_clockevent_set_next_event,
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.set_state_shutdown = npcm7xx_timer_shutdown,
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.set_state_periodic = npcm7xx_timer_periodic,
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.set_state_oneshot = npcm7xx_timer_oneshot,
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.tick_resume = npcm7xx_timer_resume,
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.rating = 300,
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},
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.of_irq = {
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.handler = npcm7xx_timer0_interrupt,
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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},
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};
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static void __init npcm7xx_clockevents_init(void)
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{
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writel(NPCM7XX_DEFAULT_CSR,
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timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR0);
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writel(NPCM7XX_Tx_RESETINT,
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timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TISR);
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npcm7xx_to.clkevt.cpumask = cpumask_of(0);
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clockevents_config_and_register(&npcm7xx_to.clkevt,
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timer_of_rate(&npcm7xx_to),
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0x1, NPCM7XX_Tx_MAX_CNT);
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}
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static void __init npcm7xx_clocksource_init(void)
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{
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u32 val;
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writel(NPCM7XX_DEFAULT_CSR,
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timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1);
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writel(NPCM7XX_Tx_MAX_CNT,
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timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TICR1);
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val = readl(timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1);
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val |= NPCM7XX_START_Tx;
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writel(val, timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1);
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clocksource_mmio_init(timer_of_base(&npcm7xx_to) +
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NPCM7XX_REG_TDR1,
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"npcm7xx-timer1", timer_of_rate(&npcm7xx_to),
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200, (unsigned int)NPCM7XX_Tx_TDR_MASK_BITS,
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clocksource_mmio_readl_down);
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}
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static int __init npcm7xx_timer_init(struct device_node *np)
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{
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int ret;
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ret = timer_of_init(np, &npcm7xx_to);
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if (ret)
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return ret;
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/* Clock input is divided by PRESCALE + 1 before it is fed */
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/* to the counter */
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npcm7xx_to.of_clk.rate = npcm7xx_to.of_clk.rate /
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(NPCM7XX_Tx_MIN_PRESCALE + 1);
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npcm7xx_clocksource_init();
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npcm7xx_clockevents_init();
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pr_info("Enabling NPCM7xx clocksource timer base: %px, IRQ: %d ",
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timer_of_base(&npcm7xx_to), timer_of_irq(&npcm7xx_to));
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return 0;
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}
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TIMER_OF_DECLARE(wpcm450, "nuvoton,wpcm450-timer", npcm7xx_timer_init);
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TIMER_OF_DECLARE(npcm7xx, "nuvoton,npcm750-timer", npcm7xx_timer_init);
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