Greentime Hu d411cf02ed riscv: fix scratch register clearing in M-mode. ... This patch fixes that the sscratch register clearing in M-mode. It cleared sscratch register in M-mode, but it should clear mscratch register. That will cause kernel trap if the CPU core doesn't support S-mode when trying to access sscratch. Fixes: 9e80635619 ("riscv: clear the instruction cache and all registers when booting") Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>		2019-12-20 03:32:24 -08:00
..
boot	riscv: Fix build dependency for loader	2019-12-08 20:19:30 -08:00
configs	Merge branch 'next/defconfig-add-debug' into for-next	2019-11-22 18:59:23 -08:00
include	pci-v5.5-changes	2019-12-03 13:58:22 -08:00
kernel	riscv: fix scratch register clearing in M-mode.	2019-12-20 03:32:24 -08:00
lib	riscv: add nommu support	2019-11-17 15:17:39 -08:00
mm	Second set of RISC-V updates for v5.5-rc1	2019-12-04 11:07:00 -08:00
net	bpf, riscv: Enable zext optimization for more RV64G ALU ops	2019-07-05 23:55:41 +02:00
Kbuild	riscv: add arch/riscv/Kbuild	2019-08-30 17:34:00 -07:00
Kconfig	riscv: Fix use of undefined config option CONFIG_CONFIG_MMU	2019-12-20 03:32:24 -08:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Kconfig.socs	riscv: only select serial sifive if TTY is enabled	2019-12-08 20:29:01 -08:00
Makefile	riscv: provide a flat image loader	2019-11-17 15:17:39 -08:00