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56c03d91f7
The PLL restore routine supports waiting pll locking. If PLL is enabled in restoring sequence, it should wait until PLL is locked. Signed-off-by: Jaecheol Lee <jc.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
473 lines
13 KiB
C
473 lines
13 KiB
C
/* linux/arch/arm/mach-exynos4/pm.c
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS4210 - Power Management support
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*
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* Based on arch/arm/mach-s3c2410/pm.c
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/suspend.h>
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#include <linux/syscore_ops.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <plat/cpu.h>
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#include <plat/pm.h>
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#include <plat/pll.h>
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#include <mach/regs-irq.h>
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#include <mach/regs-gpio.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-pmu.h>
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#include <mach/pm-core.h>
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#include <mach/pmu.h>
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static struct sleep_save exynos4_set_clksrc[] = {
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{ .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, },
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{ .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, },
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{ .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, },
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{ .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
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{ .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
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{ .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
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{ .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, },
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{ .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
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{ .reg = S5P_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
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{ .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, },
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};
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static struct sleep_save exynos4_epll_save[] = {
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SAVE_ITEM(S5P_EPLL_CON0),
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SAVE_ITEM(S5P_EPLL_CON1),
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};
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static struct sleep_save exynos4_vpll_save[] = {
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SAVE_ITEM(S5P_VPLL_CON0),
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SAVE_ITEM(S5P_VPLL_CON1),
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};
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static struct sleep_save exynos4_core_save[] = {
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/* CMU side */
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SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
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SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
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SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
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SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
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SAVE_ITEM(S5P_CLKSRC_TOP0),
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SAVE_ITEM(S5P_CLKSRC_TOP1),
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SAVE_ITEM(S5P_CLKSRC_CAM),
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SAVE_ITEM(S5P_CLKSRC_MFC),
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SAVE_ITEM(S5P_CLKSRC_IMAGE),
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SAVE_ITEM(S5P_CLKSRC_LCD0),
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SAVE_ITEM(S5P_CLKSRC_LCD1),
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SAVE_ITEM(S5P_CLKSRC_MAUDIO),
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SAVE_ITEM(S5P_CLKSRC_FSYS),
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SAVE_ITEM(S5P_CLKSRC_PERIL0),
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SAVE_ITEM(S5P_CLKSRC_PERIL1),
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SAVE_ITEM(S5P_CLKDIV_CAM),
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SAVE_ITEM(S5P_CLKDIV_TV),
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SAVE_ITEM(S5P_CLKDIV_MFC),
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SAVE_ITEM(S5P_CLKDIV_G3D),
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SAVE_ITEM(S5P_CLKDIV_IMAGE),
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SAVE_ITEM(S5P_CLKDIV_LCD0),
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SAVE_ITEM(S5P_CLKDIV_LCD1),
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SAVE_ITEM(S5P_CLKDIV_MAUDIO),
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SAVE_ITEM(S5P_CLKDIV_FSYS0),
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SAVE_ITEM(S5P_CLKDIV_FSYS1),
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SAVE_ITEM(S5P_CLKDIV_FSYS2),
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SAVE_ITEM(S5P_CLKDIV_FSYS3),
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SAVE_ITEM(S5P_CLKDIV_PERIL0),
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SAVE_ITEM(S5P_CLKDIV_PERIL1),
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SAVE_ITEM(S5P_CLKDIV_PERIL2),
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SAVE_ITEM(S5P_CLKDIV_PERIL3),
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SAVE_ITEM(S5P_CLKDIV_PERIL4),
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SAVE_ITEM(S5P_CLKDIV_PERIL5),
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SAVE_ITEM(S5P_CLKDIV_TOP),
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SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
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SAVE_ITEM(S5P_CLKSRC_MASK_TV),
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SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
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SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
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SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
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SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
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SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
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SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
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SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
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SAVE_ITEM(S5P_CLKGATE_IP_CAM),
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SAVE_ITEM(S5P_CLKGATE_IP_TV),
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SAVE_ITEM(S5P_CLKGATE_IP_MFC),
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SAVE_ITEM(S5P_CLKGATE_IP_G3D),
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SAVE_ITEM(S5P_CLKGATE_IP_IMAGE),
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SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
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SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
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SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
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SAVE_ITEM(S5P_CLKGATE_IP_GPS),
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SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
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SAVE_ITEM(S5P_CLKGATE_IP_PERIR),
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SAVE_ITEM(S5P_CLKGATE_BLOCK),
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SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
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SAVE_ITEM(S5P_CLKSRC_DMC),
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SAVE_ITEM(S5P_CLKDIV_DMC0),
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SAVE_ITEM(S5P_CLKDIV_DMC1),
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SAVE_ITEM(S5P_CLKGATE_IP_DMC),
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SAVE_ITEM(S5P_CLKSRC_CPU),
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SAVE_ITEM(S5P_CLKDIV_CPU),
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SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
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SAVE_ITEM(S5P_CLKGATE_IP_CPU),
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/* GIC side */
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SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
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SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
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SAVE_ITEM(S5P_VA_GIC_CPU + 0x008),
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SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C),
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SAVE_ITEM(S5P_VA_GIC_CPU + 0x014),
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SAVE_ITEM(S5P_VA_GIC_CPU + 0x018),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x000),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x004),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x100),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x104),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x108),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x300),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x304),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x308),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x400),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x404),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x408),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x410),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x414),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x418),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x420),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x424),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x428),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x430),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x434),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x438),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x440),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x444),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x448),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x450),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x454),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x458),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x800),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x804),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x808),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x810),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x814),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x818),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x820),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x824),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x828),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x830),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x834),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x838),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x840),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x844),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x848),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x850),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x854),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x858),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10),
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SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),
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SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000),
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SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010),
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SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020),
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SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030),
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SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040),
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SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050),
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SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060),
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SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
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SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
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SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
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};
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static struct sleep_save exynos4_l2cc_save[] = {
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SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL),
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SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL),
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SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL),
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SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL),
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SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
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};
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/* For Cortex-A9 Diagnostic and Power control register */
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static unsigned int save_arm_register[2];
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void exynos4_cpu_suspend(unsigned long arg)
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{
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outer_flush_all();
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/* issue the standby signal into the pm unit. */
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cpu_do_idle();
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/* we should never get past here */
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panic("sleep resumed to originator?");
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}
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static void exynos4_pm_prepare(void)
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{
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u32 tmp;
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s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
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s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
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s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
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s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
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tmp = __raw_readl(S5P_INFORM1);
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/* Set value of power down register for sleep mode */
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exynos4_sys_powerdown_conf(SYS_SLEEP);
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__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
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/* ensure at least INFORM0 has the resume address */
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__raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
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/* Before enter central sequence mode, clock src register have to set */
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s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
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}
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static int exynos4_pm_add(struct sys_device *sysdev)
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{
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pm_cpu_prep = exynos4_pm_prepare;
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pm_cpu_sleep = exynos4_cpu_suspend;
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return 0;
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}
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/* This function copy from linux/arch/arm/kernel/smp_scu.c */
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void exynos4_scu_enable(void __iomem *scu_base)
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{
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u32 scu_ctrl;
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scu_ctrl = __raw_readl(scu_base);
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/* already enabled? */
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if (scu_ctrl & 1)
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return;
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scu_ctrl |= 1;
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__raw_writel(scu_ctrl, scu_base);
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/*
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* Ensure that the data accessed by CPU0 before the SCU was
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* initialised is visible to the other CPUs.
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*/
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flush_cache_all();
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}
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static unsigned long pll_base_rate;
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static void exynos4_restore_pll(void)
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{
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unsigned long pll_con, locktime, lockcnt;
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unsigned long pll_in_rate;
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unsigned int p_div, epll_wait = 0, vpll_wait = 0;
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if (pll_base_rate == 0)
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return;
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pll_in_rate = pll_base_rate;
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/* EPLL */
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pll_con = exynos4_epll_save[0].val;
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if (pll_con & (1 << 31)) {
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pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
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p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
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pll_in_rate /= 1000000;
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locktime = (3000 / pll_in_rate) * p_div;
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lockcnt = locktime * 10000 / (10000 / pll_in_rate);
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__raw_writel(lockcnt, S5P_EPLL_LOCK);
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s3c_pm_do_restore_core(exynos4_epll_save,
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ARRAY_SIZE(exynos4_epll_save));
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epll_wait = 1;
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}
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pll_in_rate = pll_base_rate;
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/* VPLL */
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pll_con = exynos4_vpll_save[0].val;
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if (pll_con & (1 << 31)) {
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pll_in_rate /= 1000000;
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/* 750us */
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locktime = 750;
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lockcnt = locktime * 10000 / (10000 / pll_in_rate);
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__raw_writel(lockcnt, S5P_VPLL_LOCK);
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s3c_pm_do_restore_core(exynos4_vpll_save,
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ARRAY_SIZE(exynos4_vpll_save));
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vpll_wait = 1;
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}
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/* Wait PLL locking */
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do {
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if (epll_wait) {
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pll_con = __raw_readl(S5P_EPLL_CON0);
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if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT))
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epll_wait = 0;
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}
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if (vpll_wait) {
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pll_con = __raw_readl(S5P_VPLL_CON0);
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if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT))
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vpll_wait = 0;
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}
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} while (epll_wait || vpll_wait);
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}
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static struct sysdev_driver exynos4_pm_driver = {
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.add = exynos4_pm_add,
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};
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static __init int exynos4_pm_drvinit(void)
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{
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struct clk *pll_base;
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unsigned int tmp;
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s3c_pm_init();
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/* All wakeup disable */
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tmp = __raw_readl(S5P_WAKEUP_MASK);
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tmp |= ((0xFF << 8) | (0x1F << 1));
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__raw_writel(tmp, S5P_WAKEUP_MASK);
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pll_base = clk_get(NULL, "xtal");
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if (!IS_ERR(pll_base)) {
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pll_base_rate = clk_get_rate(pll_base);
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clk_put(pll_base);
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}
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return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver);
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}
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arch_initcall(exynos4_pm_drvinit);
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static int exynos4_pm_suspend(void)
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{
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unsigned long tmp;
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/* Setting Central Sequence Register for power down mode */
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tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
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tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
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__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
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/* Save Power control register */
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asm ("mrc p15, 0, %0, c15, c0, 0"
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: "=r" (tmp) : : "cc");
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save_arm_register[0] = tmp;
|
|
|
|
/* Save Diagnostic register */
|
|
asm ("mrc p15, 0, %0, c15, c0, 1"
|
|
: "=r" (tmp) : : "cc");
|
|
save_arm_register[1] = tmp;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void exynos4_pm_resume(void)
|
|
{
|
|
unsigned long tmp;
|
|
|
|
/*
|
|
* If PMU failed while entering sleep mode, WFI will be
|
|
* ignored by PMU and then exiting cpu_do_idle().
|
|
* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
|
|
* in this situation.
|
|
*/
|
|
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
|
|
if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
|
|
tmp |= S5P_CENTRAL_LOWPWR_CFG;
|
|
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
|
|
/* No need to perform below restore code */
|
|
goto early_wakeup;
|
|
}
|
|
/* Restore Power control register */
|
|
tmp = save_arm_register[0];
|
|
asm volatile ("mcr p15, 0, %0, c15, c0, 0"
|
|
: : "r" (tmp)
|
|
: "cc");
|
|
|
|
/* Restore Diagnostic register */
|
|
tmp = save_arm_register[1];
|
|
asm volatile ("mcr p15, 0, %0, c15, c0, 1"
|
|
: : "r" (tmp)
|
|
: "cc");
|
|
|
|
/* For release retention */
|
|
|
|
__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
|
|
__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
|
|
__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
|
|
__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
|
|
__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
|
|
__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
|
|
__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
|
|
|
|
s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
|
|
|
|
exynos4_restore_pll();
|
|
|
|
exynos4_scu_enable(S5P_VA_SCU);
|
|
|
|
#ifdef CONFIG_CACHE_L2X0
|
|
s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
|
|
outer_inv_all();
|
|
/* enable L2X0*/
|
|
writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
|
|
#endif
|
|
|
|
early_wakeup:
|
|
return;
|
|
}
|
|
|
|
static struct syscore_ops exynos4_pm_syscore_ops = {
|
|
.suspend = exynos4_pm_suspend,
|
|
.resume = exynos4_pm_resume,
|
|
};
|
|
|
|
static __init int exynos4_pm_syscore_init(void)
|
|
{
|
|
register_syscore_ops(&exynos4_pm_syscore_ops);
|
|
return 0;
|
|
}
|
|
arch_initcall(exynos4_pm_syscore_init);
|